Patents Assigned to STMicroelectronics S.A. (Casalonga)
  • Publication number: 20100108867
    Abstract: An integrated circuit includes at least one photosensitive element capable of delivering an electrical signal when light of at least one wavelength of the visible spectrum reaches it, and an electrooptic system functioning as an electrochemical shutter. The electrooptic system is located in the path of at least one light ray capable of reaching the photosensitive element and possesses at least one optical property, dependent on electrochemical reaction, that can be modified by an electrical control signal. The optical property is preferably transmission.
    Type: Application
    Filed: January 11, 2010
    Publication date: May 6, 2010
    Applicant: STMicroelectronics S.A.
    Inventors: Pierre Caubet, Michael Gros-Jean
  • Patent number: 7709916
    Abstract: An optical semiconductor device includes, in a zone (5), a structure of photosensitive diodes including a matrix (6) of lower electrodes (7), an intermediate layer (9) made of a photosensitive material formed on the matrix of lower electrodes and at least one upper electrode (10a) formed on the intermediate layer, in which an electrical connection (3a) includes at least one electrical contact pad (7a) and at least one electrical connection pad (16a) are produced beneath the intermediate layer, at least one electrical connection via (14) is produced through the intermediate layer and connects the upper electrode to the electrical contact pad and at least one well (15a) is formed outside the zone (5) and passes through at least the intermediate layer (9) in order to expose the electrical connection pad (16a). Also provided is a process for fabricating such a device.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: May 4, 2010
    Assignee: STMicroelectronics S.A.
    Inventors: Jens Prima, Francois Roy
  • Publication number: 20100102206
    Abstract: A near infrared/color photodetector made in a monolithic form in a lightly-doped substrate of a first conductivity type covering a holder and comprising a face on the side opposed to the holder. The photodetector includes at least first and second photodiodes for the storage of electric charges photogenerated in the substrate, the second photodiode being adjacent to said face; and a first region extending at least between the second photodiode and the holder, preventing the passage of said charges between a first substrate portion being located between said region and the holder and a second substrate portion extending between said face and the first region, the first photodiode being adapted to store at least charges photogenerated in the first substrate portion and the second photodiode being adapted to store charges photogenerated in the second substrate portion.
    Type: Application
    Filed: October 26, 2009
    Publication date: April 29, 2010
    Applicant: STMicroelectronics S.A.
    Inventors: Yvon Cazaux, Jérôme Vaillant
  • Patent number: 7706529
    Abstract: A random signal generator uses a folded MOS transistor, whose drain-source current includes a random component, as an electronic noise source. The random signal generator generates a random binary signal from the random component. The invention may be applied, in particular, to smart cards.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: April 27, 2010
    Assignee: STMicroelectronics S.A.
    Inventors: Fabrice Marinet, Alexandre Malherbe
  • Patent number: 7704630
    Abstract: A support wafer made of silicon wafer comprising, on a first surface a porous silicon layer having protrusions, porous silicon pillars extending from the porous silicon layer to the second surface of the wafer, in front of each protrusion. Layers constituting a fuel cell can be formed on the support wafer.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: April 27, 2010
    Assignee: STMicroelectronics S.A.
    Inventor: Sébastien Kouassi
  • Patent number: 7704757
    Abstract: A method is provided for manufacturing an integrated electronic component arranged on a substrate wafer. According to the method, at least one metallization step is performed, and a value of an electrical parameter of the integrated electronic component is determined after the at least one metallization step. A subsequent metallization step is performed after determining the value of the electrical parameter. The subsequent metallization step is performed using an adjustment mask chosen from n predefined masks based on a desired value of the electrical parameter, so as to obtain the desired value of the electrical parameter of the integrated electronic component after manufacturing. In one preferred embodiment, a series of electrical tests is performed on the wafer using test equipment, and the value of the electrical parameter is determined using the same test equipment as is used to perform the series of electrical tests.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: April 27, 2010
    Assignee: STMicroelectronics S.A.
    Inventors: Francis Dell'Ova, Frank Lhermet, Dominique Poirot, Stephane Rayon, Bertrand Gomez, Nicole Lessoile, Pierre Rizzo
  • Patent number: 7705905
    Abstract: An image sensor pixel structure including: a photosensitive area surrounded with a peripheral area placed at the surface of a semiconductor substrate, a stack of several insulating layers alternately exhibiting different refraction coefficients and placed above the peripheral area, a microlens placed at the top of the pixel to have the pixel light converge towards the photosensitive area, and a transparent block placed substantially above the photosensitive area.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: April 27, 2010
    Assignee: STMicroelectronics S.A.
    Inventor: Jérôme Vaillant
  • Publication number: 20100097093
    Abstract: Circuitry including an output circuit having a first variable resistance block coupled between a first supply voltage and an output node, the first variable resistance block having a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the output node, the output circuit having an output impedance determined by the resistance of the first variable resistance block; and a compensation circuit for regulating the impedance of the first variable resistance block of the output circuit, the compensation circuit having a second variable resistance block coupled between the first supply voltage and the first node of an external resistor, the second node of the external resistor being coupled to a second supply voltage, wherein the second variable resistance block comprises a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the first node of the external resistor, and wher
    Type: Application
    Filed: October 15, 2009
    Publication date: April 22, 2010
    Applicant: STMicroelectronics S.A.
    Inventors: Nicolas Ricard, Laurent Jean Garcia
  • Publication number: 20100097843
    Abstract: An integrated cell and method for extracting a binary value based on a value difference between two resistors values, including connection circuitry for a binary reading of the sign of the difference between the resistors, and connection circuitry for a modification of the value of one of the resistors to make the sign of the difference invariable.
    Type: Application
    Filed: December 18, 2009
    Publication date: April 22, 2010
    Applicant: STMicroelectronics S.A.
    Inventors: Michel Bardouillet, Pierre Rizzo, Alexandre Malherbe, Luc Wuidart
  • Patent number: 7701047
    Abstract: An integrated-circuit chip includes a first electrical connection are placed on an underlying layer and covered with an intermediate dielectric layer. A second electrical connection is placed on the intermediate dielectric layer and is covered with a superficial dielectric layer. External electrical connection pads are placed on the superficial dielectric layer and extend selectively over the first electrical connection. Vias pass through the superficial dielectric layer and the intermediate dielectric layer to make connection between the first electrical connection and the external electrical connection pads.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: April 20, 2010
    Assignees: STMicroelectronics S.A., STMicroelectronics S.r.l.
    Inventors: Olivier Le Briz, Sébastien Marsanne, Laurence Martin, Guiseppe Croce
  • Patent number: 7700970
    Abstract: An integrated power device includes a semiconductor body of a first conductivity type comprising a first region accommodating a start-up structure, and a second region accommodating a power structure. The two structures are separated from one another by an edge structure and are arranged in a mirror configuration with respect to a symmetry line of the edge structure. Both the start-up structure and the power structure are obtained using MOSFET devices. Both MOSFET devices are multi-drain MOSFET devices, having mesh regions, source regions and gate regions separated from one another. In addition, both MOSFET devices have drain regions delimited by columns that repeat periodically at a fixed distance. Between the two MOSFET devices there is an electrical insulation of at least 25 V.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: April 20, 2010
    Assignees: STMicroelectronics S.r.l., STMicroelectronics S.A.
    Inventors: Mario Giuseppe Saggio, Antonino Longo Minnolo, Rosalia Germana'
  • Patent number: 7700981
    Abstract: The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of capacitive elements having at least an electrode formed of a conductive bidimensional perovskite forming an interface between said dielectric and an underlying silicon, metal, or amorphous oxide substrate.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: April 20, 2010
    Assignee: STMicroelectronics S.A. Universite Francois Rabelais
    Inventors: Ludovic Goux, Monique Gervais
  • Patent number: 7697636
    Abstract: A process of correction of the spectral inversion for a receiver in a digital communication system: the process allows the reception in the receiver of a training sequence presumably known according to a modulation of type ?/2 BPSK or MDP2. The process includes the following steps: Demodulating of the training sequence; Calculating of the differential correlation on a set of N received samples (Rn) and presumably sent (Sn) to generate a result; Using the result to detect the beginning of the frame and to order a spectral inversion in the chain of reception of the aforementioned receiver before launching the detection of the beginning of the frame. A receiver to process automatically the spectral inversion is also described.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 13, 2010
    Assignee: STMicroelectronics S.A.
    Inventor: Jacques Meyer
  • Patent number: 7691727
    Abstract: A method for manufacturing an integrated circuit containing fully and partially depleted MOS transistors, including the steps of forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate; attaching the upper surface of the structure to a support wafer; eliminating the substrate; depositing a mask and opening this mask at the locations of the fully-depleted transistors; oxidizing the silicon-germanium at the locations of the fully-depleted transistors in conditions such that a condensation phenomenon occurs; and eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: April 6, 2010
    Assignees: STMicroelectronics S.A., STMicroelectronics Crolles 2 SAS
    Inventors: Philippe Coronel, Michel Marty
  • Patent number: 7692262
    Abstract: A vertical rectifying and protection power diode, formed in a lightly-doped semiconductor layer of a first conductivity type, resting on a heavily-doped substrate of the first conductivity type, having a first ring-shaped region, of the first conductivity type more heavily-doped than the layer and more lightly doped than the substrate, surrounding an area of the layer and extending to the substrate; and a second ring-shaped region, doped of the second conductivity type, extending at the surface of the first region and on either side thereof; a first electrode having a thin layer of a material capable of forming a Schottky diode with the layer, resting on the area of the layer and on at least a portion of the second ring-shaped region with which it forms an ohmic contact.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: April 6, 2010
    Assignee: STMicroelectronics S.A.
    Inventors: Jean-Luc Morand, Emmanuel Collard, André Lhorte
  • Publication number: 20100078673
    Abstract: A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.
    Type: Application
    Filed: December 7, 2009
    Publication date: April 1, 2010
    Applicant: STMicroelectronics S.A.
    Inventor: Jean-Luc Morand
  • Patent number: 7687399
    Abstract: A semiconductor product includes a portion made of copper, a portion made of a dielectric and a self-aligned barrier between the copper portion and the dielectric portion. The self-aligned barrier includes a first copper silicide layer comprising predominantly first copper silicide molecules, and a second copper silicide layer comprising predominantly second copper silicide molecules. The proportion of the number of silicon atoms is higher in the second silicide molecules than in the first silicide molecules. The second copper silicide layer is positioned between the copper portion and the first copper silicide layer. A nitride layer may overlie at least part of the first copper silicide layer.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: March 30, 2010
    Assignee: STMicroelectronics S.A.
    Inventors: Pierre Caubet, Nicolas Casanova
  • Patent number: 7689636
    Abstract: A method and a circuit for normalizing a noise source providing an initial bit flow, including conditioning the state of an output bit to the respective states of the bits of the initial flow examined by words of identical lengths and, upon occurrence of a word of bits of identical states, conditioning the state of the current output bit to the state of at least one previous output bit.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: March 30, 2010
    Assignee: STMicroelectronics S.A.
    Inventors: Pierre-Yvan Liardet, Yannick Teglia, Ambroise Tomei
  • Patent number: 7687819
    Abstract: An optical semiconductor package includes a support with a passage to receive a ring holding a lens situated facing an optical sensor. The support has, in the passage, at least one local release recess and the ring is equipped peripherally with a locally projecting, elastically deformable element. The local release recess and the elastically deformable element are such that, when the ring occupies an angular mounting position, the locally projecting elastically deformable element is engaged in the local recess of the support and, when the ring is pivoted from the aforementioned angular mounting position, the locally projecting elastically deformable element is moved out of the recess of the support and is compressed against the wall of the passage in order to secure the ring relative to the support.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: March 30, 2010
    Assignee: STMicroelectronics S.A.
    Inventor: Julien Vittu
  • Patent number: RE41179
    Abstract: A device for extracting parameters for decoding a video data flow, contained in headers preceded by a starting code of series of data coded according to an MPEG standard, organized, independently and according to the starting code, and storage of the parameters in three register banks.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: March 30, 2010
    Assignee: STMicroelectronics S.A.
    Inventor: Philippe Monnier