Patents Assigned to STMicroelectronics, S.r.I.
  • Publication number: 20120217947
    Abstract: A voltage converter device includes a voltage regulator having a supply terminal for receiving a supply voltage and an output terminal for providing a regulated voltage. A voltage multiplier is for receiving the regulated voltage and providing a boosted voltage higher in absolute value than the regulated voltage. The voltage multiplier includes circuitry for providing a clock signal that switches periodically between the regulated voltage and a reference voltage, and a sequence of capacitive stages that alternately accumulate and transfer electric charge according to the clock signal for generating the boosted voltage from the regulated voltage. The voltage regulator includes a power transistor and a regulation transistor each having a first conduction terminal, a second conduction terminal and a control terminal.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 30, 2012
    Applicant: STMicroelectronics, S.r.I.
    Inventors: MARIO MICCICHE, Antonio Conte, Carmelo Ucciardello, FrancescoNino Mammoliti
  • Publication number: 20110135031
    Abstract: A pulse generator circuit is provided. The pulse generator circuit has an input adapted to receive an input electrical quantity and an output at which an output electrical quantity is made available. A transfer characteristic establishes a relationship between said input and said output electrical quantities. The pulse generator circuit is adapted to provide said output electrical quantity in the form of pulses having a predetermined shape, suitable to be used for UWB transmission. The transfer characteristic has substantially a same shape as that of said pulses. Moreover, a UWB modulating system exploiting the novel pulse generator is proposed.
    Type: Application
    Filed: December 6, 2010
    Publication date: June 9, 2011
    Applicant: STMicroelectronics, S.r.I.
    Inventors: Marco Orazio CAVALLARO, Tino Copani, Giovanni Girlando, Giuseppe Palmisano
  • Publication number: 20110134966
    Abstract: A pulse generator circuit is provided. The pulse generator circuit has an input adapted to receive an input electrical quantity and an output at which an output electrical quantity is made available. A transfer characteristic establishes a relationship between said input and said output electrical quantities. The pulse generator circuit is adapted to provide said output electrical quantity in the form of pulses having a predetermined shape, suitable to be used for UWB transmission. The transfer characteristic has substantially a same shape as that of said pulses. Moreover, a UWB modulating system exploiting the novel pulse generator is proposed.
    Type: Application
    Filed: December 6, 2010
    Publication date: June 9, 2011
    Applicant: STMicroelectronics, S.r.I.
    Inventors: Marco Orazio CAVALLARO, Tino Copani, Giovanni Girlando, Giuseppe Palmisano
  • Publication number: 20110110169
    Abstract: A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line which is connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of a reading operation of the data stored into the memory cell, the evaluation circuit comprising a negative feedback control loop adapted to control the potential of the bit line during the sensing phase, the control loop comprising a differential amplifier having an inverting input terminal operatively connected to the bit line, a non-inverting input terminal fed by a first reference potential, and a feedback circuital path connected between an output of the differential amplifier and the inverting input, wherein the feedback circuital path is adapted to conduct a measure current corresponding to the cell electric current, and comprises current/voltage conversion means for converting the measure current into a corresponding
    Type: Application
    Filed: October 25, 2010
    Publication date: May 12, 2011
    Applicant: STMicroelectronics, S.r.I.
    Inventors: Antonio GIAMBARTINO, Michele La Placa, Ignazio Martines
  • Publication number: 20100006856
    Abstract: A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions within the polycrystalline silicon laterally with respect to the gate structures. The crystallizing step includes forming first capping dielectric regions on the amorphous silicon layer, and then irradiating the amorphous silicon layer using a laser so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying the first capping dielectric regions.
    Type: Application
    Filed: September 22, 2009
    Publication date: January 14, 2010
    Applicant: STMicroelectronics, S.r.I.
    Inventors: Salvatore LEONARDI, Claudia Caligiore
  • Publication number: 20090070056
    Abstract: Measurements are acquired from a magnetic sensor during a non-pre-ordered movement, and a plurality of sets of solutions are determined for respective expected values of intensity of the Earth's magnetic field. The solutions are defined by a plurality of parameters, including at least one gain value for each detection axis of the magnetic sensor. For each solution, a figure of merit is determined, correlated to a calibration error, and a partial solution is selected in each set of solutions, based on the figure of merit. Once a gain confidence interval has been defined, a calibration solution is selected based on the figure of merit, from among the partial solutions having respective gain values all falling within the gain confidence interval.
    Type: Application
    Filed: August 22, 2008
    Publication date: March 12, 2009
    Applicant: STMicroelectronics, S.r.I.
    Inventors: Francesco Vocali, Fabio Biganzoli
  • Patent number: 7012832
    Abstract: A magnetic random access memory (MRAM) device has increased ?R/R for sensing a state of a pin-dependent tunneling (SDT) device. The MRAM device includes plural transistors connected to a read line for sensing the state of the SDT device. Plural transistors lower an underlying resistance during reading, increasing ?R/R. The plural transistors can share a source region.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: March 14, 2006
    Assignees: WEstern Digital (Fremont), Inc., STMicroelectronics, S.r.I.
    Inventors: Kyusik Sin, Matthew R. Gibbons, William D. Jensen, Hugh Craig Hiner, Xizeng Stone Shi, Roberto Bez, Giulio Casagrande, Paolo Cappelletti
  • Publication number: 20030201503
    Abstract: MOS-gated power device including a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type. A plurality of doped regions of a first conductivity type is formed in the semiconductor material layer, each one of the doped regions being disposed under a respective body region and being separated from other doped regions by portions of the semiconductor material layer.
    Type: Application
    Filed: May 6, 2003
    Publication date: October 30, 2003
    Applicant: STMicroelectronics, S.r.I.
    Inventor: Ferruccio Frisina
  • Publication number: 20030026498
    Abstract: The conversion into a progressive format of digital images organized in half-frames or fields with interlaced lines or rows envisages selecting successive lines in one or more of said fields and reconstructing by pixels an image line set between the interlaced lines selected. The reconstruction operation obtains the image by creating a set of candidate patterns associated to the work window by selecting the patterns to be considered within the window. Next, applying to the patterns of the aforesaid set a first cost function which is representative of the correlations between pairs of pixels. Applying to the patterns of the aforesaid set a second cost function which is representative of the non-correlations between pairs of pixels. Selecting, for each candidate pattern, respective internal correlations and external non-correlations, calculating corresponding scores for the candidate patterns using the aforesaid first cost function.
    Type: Application
    Filed: June 14, 2002
    Publication date: February 6, 2003
    Applicant: STMicroelectronics, S.r.I.
    Inventors: Daniele Sirtori, Matteo Maravita
  • Publication number: 20020186774
    Abstract: A process and a system is described for generating an MPEG output bitstream starting from an MPEG input bitstream. The output bitstream has a resolution modified with respect to the resolution of the input bitstream. -In the input bitstream, first portions that substantially do not affect and second portions that do affect resolution variation are distinguished. The second portions are then subjected to a function of modification of the resolution obtained by filtering the second portions in a domain of the discrete cosine transform, and then are transferred to the output bitstream. A corresponding computer program product is also provided.
    Type: Application
    Filed: February 11, 2002
    Publication date: December 12, 2002
    Applicant: STMicroelectronics, S.r.I.
    Inventors: Danilo Pau, Daniele Alfonso, Fabrizio Basso, Emiliano Piccinelli, Alessandro Cremonesi
  • Publication number: 20020159528
    Abstract: In order to generate, starting from an input MPEG bitstream, an output MPEG bitstream having at least one entity chosen among syntax, resolution, and bitrate modified with respect to the input bitstream, first portions and second portions are distinguished in the input bitstream, which respectively substantially do not affect and do affect the variation in bitrate. When at least one between the syntax and the resolution is to be modified, the first portions of the input bitstream are subjected to the required translation, then transferring said first portions subjected to syntax and/or resolution translation to the output bitstream. When the resolution is left unaltered, the second portions are transferred from the input bitstream to the output bitstream in the substantial absence of processing operations. When the resolution is changed, the second portions of the input bitstream are subjected to a filtering in the domain of the discrete cosine transform.
    Type: Application
    Filed: February 8, 2002
    Publication date: October 31, 2002
    Applicant: STMicroelectronics, S.r.I.
    Inventors: Andrea Graziani, Luca Celetto, Daniele Alfonso, Fabrizio Basso, Alessandro Cremonesi, Danilo Pau
  • Publication number: 20020130334
    Abstract: An electrically-modifiable, non-volatile, semiconductor memory comprising a plurality of user memory locations which can be addressed individually from outside the memory in order to read and to modify the data held therein is characterized in that, for each user memory location, there is a corresponding pair of physical memory locations in the memory, which assume, alternatively, the functions of an active memory location and of a non-active memory location, the active memory location containing a previously-written datum and the non-active memory location being available for the writing of a new datum to replace the previously-written datum, so that, upon a request to replace the previous datum with the new datum, the previous datum is kept in the memory until the new datum has been written.
    Type: Application
    Filed: December 28, 2001
    Publication date: September 19, 2002
    Applicant: STMicroelectronics, S.r.I.
    Inventors: Roberto Gastaldi, Gianbattsista Lo Giudice, Marco Pasotti, Federico Pio
  • Publication number: 20020074607
    Abstract: A bipolar transistor is produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and is part of an integrated circuit. The integrated circuit includes a semiconductor substrate having a first type of conductivity, a PMOS transistor formed in said substrate, an NMOS transistor formed in said substrate, and the bipolar transistor.
    Type: Application
    Filed: February 15, 2002
    Publication date: June 20, 2002
    Applicant: STMicroelectronics, S.r.I.
    Inventors: Loris Vendrame, Paolo Ghezzi