Abstract: A transmission channel includes at least one high voltage buffer block having buffer transistors and respective buffer diodes, being electrically coupled between respective voltage reference terminals, these buffer transistors being also coupled to a clamping block, in turn including clamping transistors connected to at least one output terminal of this transmission channel through diodes coupled to prevent the body diodes of the clamping transistors from conducting. The transmission channel includes at least one reset circuit having diodes and being electrically coupled between circuit nodes of the high voltage buffer block and of the clamping block, these circuit nodes being in correspondence with conduction terminals of the transistors comprised into the high voltage buffer block and into the clamping block.

Abstract: A method for manufacturing a HEMT transistor includes: realizing an undoped epitaxial layer on a substrate; realizing a barrier epitaxial layer on the undoped epitaxial layer so as to form a heterojunction; realizing source and drain structures, separated from one other, on the barrier epitaxial layer; depositing an insulating layer on the barrier epitaxial layer and on the source and drain structures; and photolithographic defining the insulating layer, defining first and second insulating portions in correspondence of the source and drain structures, respectively, and exposing a portion of the barrier epitaxial layer. The method further comprises: forming first and second spacers lying at the corners of the first and second insulating portions; and depositing a gate metal structure at least partially covering said first and second insulating portions, and said first and second spacers, said gate metal structure being a field plate of the HEMT transistor.

Abstract: A generator of a voltage logarithmically variable with temperature may include a differential amplifier having a pair of transistors, each coupled with a respective bias network adapted to bias in a conduction state the transistors first and second respectively with a constant current and with a current proportional to the working absolute temperature. The pair of transistors may generate between their control nodes the voltage logarithmically variable with temperature. The differential amplifier may have a common bias current generator coupled between the common terminal of the differential pair of transistors and a node at a reference potential, and a feedback line to provide a path for the current difference between the sum of currents flowing through the transistors of the differential pair and the common bias current.

Abstract: A confocal optical detector including a light source generating a first optical beam along an axis; an optoelectronic sensor; an optical focusing device, which receives and focuses the first optical beam; and a hole, which receives the first optical beam and is arranged between the optoelectronic sensor and the optical focusing device. The optoelectronic sensor is arranged between the light source and the hole. In addition, the optoelectronic sensor and the optical focusing device are aligned along the axis.

Abstract: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.

Abstract: An embodiment of a method for manufacturing a power device being integrated on a semiconductor substrate comprising at least the steps of making, in the semiconductor substrate, at least a trench having sidewalls and a bottom, covering the sidewalls and the bottom of said at least one trench with a first insulating coating layer and making, inside said at least one trench, a conductive gate structure. An embodiment of the method provides the formation of the conductive gate structure comprising the steps of covering at least the sidewalls with a second conductive coating layer of a first conductive material; making a conductive central region of a second conductive material having a different resistivity than the first conductive material; and making a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

Abstract: A voltage converter device includes a voltage regulator having a supply terminal for receiving a supply voltage and an output terminal for providing a regulated voltage. A voltage multiplier is for receiving the regulated voltage and providing a boosted voltage higher in absolute value than the regulated voltage. The voltage multiplier includes circuitry for providing a clock signal that switches periodically between the regulated voltage and a reference voltage, and a sequence of capacitive stages that alternately accumulate and transfer electric charge according to the clock signal for generating the boosted voltage from the regulated voltage. The voltage regulator includes a power transistor and a regulation transistor each having a first conduction terminal, a second conduction terminal and a control terminal.

Abstract: An address decoding device may include a supply terminal for a supply voltage, a conductive path configured to provide an electric signal, associated with an address of at least one memory cell, and an address terminal connected to the conductive path and structured to receive the electric signal. An address decoder may be connected to the address terminal to receive the electric signal. The decoder may have a decoding operative voltage associated therewith. A switch circuit may be structured to electrically connect the address terminal to the supply terminal when the address terminal takes a threshold voltage imposed by the electric signal, and may bring the address terminal to the decoding operative voltage.

Abstract: A method for non-destructive reading of logic data stored in a memory includes applying to a first wordline a reading voltage so as not to cause a variation of the stable state of polarization of a layer of ferroelectric material, and generating a difference of potential between first and second bitlines. An output current is generated comparing the output current with a plurality of comparison values, and determining the logic value of the logic data to be read on the basis of the comparison.

Abstract: Logic data is written in a memory having a first word line and a first bit line, with the memory including a first memory cell having a first ferroelectric transistor. The first ferroelectric transistor includes a layer of ferroelectric material and has a first conduction terminal coupled to the first bit line, and a control terminal coupled to the first word line. The logic data is written based on biasing the control terminal of the first ferroelectric transistor at a first biasing value, biasing the first conduction terminal of the first ferroelectric transistor at a second biasing value different from the first biasing value, and generating a stable variation of the state of polarization of the layer of ferroelectric material of the first ferroelectric transistor to write the logic data in the first memory cell.

Abstract: A control device of a driving circuit of a discharge lamp is described. The driving circuit comprises an half bridge with a high side and a low side switches and the control device comprises a first device configured to control the switching frequency of the half bridge and a second device configured to detect the saturation current condition of the choke or the over current condition by detecting, cycle by cycle, a signal representative of the current passing through the low side switch. The second device generate a signal to cause the turning off of the low side switch and the turning on of the high side switch when the saturation current or over current condition of the choke is detected.

Abstract: A voltage booster device may include a plurality of multiplication stages arranged in a sequence so that an input terminal of each multiplication stage, with the exception of a first multiplication stage, is connected to an output terminal of a previous multiplication stage. Each multiplication stage may include pumping circuitry for accumulating an electric charge proportional to a pump voltage value of the multiplication stage. Each multiplication stage may also include a phase signal generating circuit for switching the multiplication stages between a transfer phase and a maintaining phase. In at least one of the stages, the pumping circuitry may include at least two series connected charge accumulators. A terminal may be shared between the charge accumulators and may be connected through biasing circuitry to an output terminal of a previous multiplication stage for forcing the charge accumulators within a threshold potential drop value.

Abstract: An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with a respective main bit line. Each local bit line is selectively couplable to the respective main bit line by a corresponding selector. Each local bit line is selectively couplable to a reference terminal, for receiving a reference voltage, by a corresponding discharge selector. Each discharge selector is active when the memory device is in a standby state. The non-volatile memory device further includes biasing circuitry to bias each main bit line to a pre-charge voltage during operation, and reading circuitry to select and access a group of memory cells during reading operations.

Abstract: An embodiment of a photomultiplier device is formed by a base substrate of insulating organic material forming a plurality of conductive paths and carrying a plurality of chips of semiconductor material. Each chip integrates a plurality of photon detecting elements, such as Geiger-mode avalanche diodes, and is bonded on a first side of the base substrate. Couplings for photon-counting and image-reconstruction units are formed on a second side of the base substrate. The first side of the base substrate is covered with a transparent encapsulating layer of silicone resin, which, together with the base substrate, bestows stiffness on the photomultiplier device, preventing warpage, and covers and protects the chips.

Abstract: A system for identifying a plurality of components of a vehicle that includes a plurality of non-volatile memories for storing identifiers associated with the plurality of vehicle components, a controller of the plurality of the vehicle components, a communication network configured for connecting the controller to the plurality of memories, and an identifiers memory including a portion to store a list of a plurality of type-approved identifiers associated with the plurality of type-approved vehicle components. The controller receives the identifiers, reads from the portion of the identifiers memory the list of type-approved identifiers, and checks if the identifiers of the plurality of components are included in the list of the type-approved identifiers, and when the controller detects that an identifier associated with a component out of the plurality of components is not included in the list, the controller blocks operation of the component.

Abstract: A process is described for integrating two closely spaced thin films without deposition of the films through deep vias. The films may be integrated on a wafer and patterned to form a microscale heat-trimmable resistor. A thin-film heating element may be formed proximal to a thin-film resistive element, and heat generated by the thin-film heater can be used to permanently trim a resistance value of the thin-film resistive element. Deposition of the thin films over steep or abrupt topography is minimized by using a process in which the thin films are deposited in a sequence that falls between depositions of thick metal contacts to the thin films.

Abstract: A method for carrying out nucleic acid amplification, includes providing a reaction chamber (31), accommodating an array (36) of nucleic acid probes (37) at respective locations, for hybridizing to respective target nucleic acids; and introducing a solution (50) into the reaction chamber (31), wherein the solution (50) contains primers, capable of binding to target nucleic acids, nucleotides, nucleic acid extending enzymes and a sample including nucleic acids. The a structure of the nucleic acid probes (37) and of the primers so that a hybridization temperature (TH) of the probes (37) is higher than an annealing temperature (TA) of the primers, whereby hybridization and annealing take place in respective separate temperature ranges (RH, RA).

Abstract: A solar energy plant may include a DC bus, photovoltaic panels coupled in parallel to the DC bus, each photovoltaic panel having a DC/DC converter, and a first controller controlling the DC/DC converter depending on whether a voltage on the DC bus is equal to or greater than a first threshold and lower than or equal to a second threshold. The solar energy plant may include a DC/AC inverter coupled to the DC bus and outputting an output AC voltage, an auxiliary start-up power supply charging a parasitic capacitance on the DC bus up to the first threshold, and a second controller turning on the auxiliary start-up power supply based upon a start command, and turning off the auxiliary start-up power supply and simultaneously turning on the DC/AC inverter.

Abstract: The voltage regulators are capable of limiting undershoots of the output voltage without having a similar effect on overshoots because of the presence of a current cancellation network, input with the reference voltage and coupled to the second input of the error amplifier. This current cancellation network is adapted to inject into the second input a unidirectional compensation current of the first and second currents injected by the first and second feedback networks, respectively, the compensation current being determined by time variations of the difference between a replica of the output regulated voltage and the reference voltage and/or by time variations of the reference voltage.

Abstract: A memory base cell stores a bit of information implemented from a regular and compact structure made up of multiple identical and replicated base elements, on the “sea of gates” Model, in which the base element of the structure is a cell able to be configured with a minimum width in relation to the particular technology used. Such a cell includes a bistable element with an input node operatively connected to a writing data line of the memory base cell, and an output node operatively connected to a reading data line of the memory base cell. The bistable element also has a first inverter and a second inverter arranged in a feedback configuration with respect to one another between the input node and the output node of the bistable element.