Abstract: An analyzer for biochemical analyses includes a seat for receiving a recipient. A first light source and a second light source illuminate the recipient with a luminous radiation, respectively, in a first excitation band and in a second excitation band, including a first excitation wavelength and a second excitation wavelength of fluorophores of a first type and of a second type. A first image sensor and a second image sensor are oriented so as to receive light emitted by fluorophores contained in the recipient and are, respectively, provided with a first detection filter and a second detection filter, having, respectively, a first detection passband and a second detection passband, including, respectively, a first emission wavelength and a second emission wavelength of the fluorophores of the first type and of the second type.

Abstract: A semiconductor device may have a thickness, such that the semiconductor devices are not flexible, and may be bonded and electrically coupled on a flexible substrate. After this bonding, the semiconductor device may be thinned so as to be rendered flexible.

Abstract: An analog-to-digital converter device may include an input multiplexer circuit having analog input terminals configured to receive a respective plurality of analog input signals. The input multiplexer circuit may be responsive to a first select input. The device may also include a trigger multiplexer circuit having input terminals configured to receive respective triggering signals. The trigger multiplexer circuit may be responsive to a second select input. Analog-to-digital converter circuitry may be configured to convert the selected analog signal into a digital signal. A sequence arbiter may be coupled to the first and second select inputs and may have input terminals configured to receive a respective plurality of conversion sequence configuration signals. The sequence arbiter may be configured to manage each conversion sequence of the analog-to-digital converter circuitry based upon the relative conversion sequence configuration signal received, and control the conversion sequences.

Abstract: The trimming circuit includes a plurality of trimmable resistances that may be coupled among them, each resistance being connected in parallel to a respective fuse. The trimming circuit allows burning any number of fuses according to a fixed trimming sequence using only one or two dedicated pins because it includes an input diode-connected transistor and a plurality of trimming transistors of different sectional area, each connected to force current throughout a respective one of the shunt fuses and coupled to the input diode-connected transistor such to mirror the current flowing therethrough. The fuses of the trimming circuit may be burnt by applying a trimming voltage to the diode-connected input transistor with a voltage generator connected between a dedicated pin of the circuit and a terminal at a reference potential, such to force a current therethrough as long as the mirrored currents flowing throughout the fuses burn them.

Abstract: A method of performing a cryptographic operation including: receiving a plurality of binary input values; splitting the binary input values into a plurality of non-binary digits of base r, where r is an integer greater than 2 and not equal to a power of 2; and performing, by a cryptographic block on each of the plurality of non-binary digits, a different modulo r operation to generate at least one output digit) of base r.

Abstract: A biasing circuit may include an input configured to receive a supply voltage, a value of which is higher than a limit voltage. The biasing circuit may also include a control stage configured to generate first and second control signals with mutually complementary values, equal alternatively to a first value, in a first half-period of a clock signal, or to a second value, in a second half-period of the clock signal. The first and second values may be a function of the supply and limit voltages. The biasing circuit may also include a biasing stage configured to generate a biasing voltage as a function of the values of the first and second control signals. The first and second control signals may control transfer transistors for transferring the supply voltage to respective outputs, while the biasing voltage may be for controlling protection transistors to reduce overvoltages on the transfer transistors.

Abstract: A method for manufacturing a HEMT transistor includes: realizing an undoped epitaxial layer on a substrate; realizing a barrier epitaxial layer on the undoped epitaxial layer so as to form a heterojunction; realizing source and drain structures, separated from one other, on the barrier epitaxial layer; depositing an insulating layer on the barrier epitaxial layer and on the source and drain structures; and photolithographic defining the insulating layer, defining first and second insulating portions in correspondence of the source and drain structures, respectively, and exposing a portion of the barrier epitaxial layer. The method further comprises: forming first and second spacers lying at the corners of the first and second insulating portions; and depositing a gate metal structure at least partially covering said first and second insulating portions, and said first and second spacers, said gate metal structure being a field plate of the HEMT transistor.

Abstract: A generator of a voltage logarithmically variable with temperature may include a differential amplifier having a pair of transistors, each coupled with a respective bias network adapted to bias in a conduction state the transistors first and second respectively with a constant current and with a current proportional to the working absolute temperature. The pair of transistors may generate between their control nodes the voltage logarithmically variable with temperature. The differential amplifier may have a common bias current generator coupled between the common terminal of the differential pair of transistors and a node at a reference potential, and a feedback line to provide a path for the current difference between the sum of currents flowing through the transistors of the differential pair and the common bias current.

Abstract: A confocal optical detector including a light source generating a first optical beam along an axis; an optoelectronic sensor; an optical focusing device, which receives and focuses the first optical beam; and a hole, which receives the first optical beam and is arranged between the optoelectronic sensor and the optical focusing device. The optoelectronic sensor is arranged between the light source and the hole. In addition, the optoelectronic sensor and the optical focusing device are aligned along the axis.

Abstract: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.

Abstract: An address decoding device may include a supply terminal for a supply voltage, a conductive path configured to provide an electric signal, associated with an address of at least one memory cell, and an address terminal connected to the conductive path and structured to receive the electric signal. An address decoder may be connected to the address terminal to receive the electric signal. The decoder may have a decoding operative voltage associated therewith. A switch circuit may be structured to electrically connect the address terminal to the supply terminal when the address terminal takes a threshold voltage imposed by the electric signal, and may bring the address terminal to the decoding operative voltage.

Abstract: A voltage converter device includes a voltage regulator having a supply terminal for receiving a supply voltage and an output terminal for providing a regulated voltage. A voltage multiplier is for receiving the regulated voltage and providing a boosted voltage higher in absolute value than the regulated voltage. The voltage multiplier includes circuitry for providing a clock signal that switches periodically between the regulated voltage and a reference voltage, and a sequence of capacitive stages that alternately accumulate and transfer electric charge according to the clock signal for generating the boosted voltage from the regulated voltage. The voltage regulator includes a power transistor and a regulation transistor each having a first conduction terminal, a second conduction terminal and a control terminal.

Abstract: Logic data is written in a memory having a first word line and a first bit line, with the memory including a first memory cell having a first ferroelectric transistor. The first ferroelectric transistor includes a layer of ferroelectric material and has a first conduction terminal coupled to the first bit line, and a control terminal coupled to the first word line. The logic data is written based on biasing the control terminal of the first ferroelectric transistor at a first biasing value, biasing the first conduction terminal of the first ferroelectric transistor at a second biasing value different from the first biasing value, and generating a stable variation of the state of polarization of the layer of ferroelectric material of the first ferroelectric transistor to write the logic data in the first memory cell.

Abstract: A method for non-destructive reading of logic data stored in a memory includes applying to a first wordline a reading voltage so as not to cause a variation of the stable state of polarization of a layer of ferroelectric material, and generating a difference of potential between first and second bitlines. An output current is generated comparing the output current with a plurality of comparison values, and determining the logic value of the logic data to be read on the basis of the comparison.

Abstract: A voltage booster device may include a plurality of multiplication stages arranged in a sequence so that an input terminal of each multiplication stage, with the exception of a first multiplication stage, is connected to an output terminal of a previous multiplication stage. Each multiplication stage may include pumping circuitry for accumulating an electric charge proportional to a pump voltage value of the multiplication stage. Each multiplication stage may also include a phase signal generating circuit for switching the multiplication stages between a transfer phase and a maintaining phase. In at least one of the stages, the pumping circuitry may include at least two series connected charge accumulators. A terminal may be shared between the charge accumulators and may be connected through biasing circuitry to an output terminal of a previous multiplication stage for forcing the charge accumulators within a threshold potential drop value.

Abstract: An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with a respective main bit line. Each local bit line is selectively couplable to the respective main bit line by a corresponding selector. Each local bit line is selectively couplable to a reference terminal, for receiving a reference voltage, by a corresponding discharge selector. Each discharge selector is active when the memory device is in a standby state. The non-volatile memory device further includes biasing circuitry to bias each main bit line to a pre-charge voltage during operation, and reading circuitry to select and access a group of memory cells during reading operations.

Abstract: An embodiment of a photomultiplier device is formed by a base substrate of insulating organic material forming a plurality of conductive paths and carrying a plurality of chips of semiconductor material. Each chip integrates a plurality of photon detecting elements, such as Geiger-mode avalanche diodes, and is bonded on a first side of the base substrate. Couplings for photon-counting and image-reconstruction units are formed on a second side of the base substrate. The first side of the base substrate is covered with a transparent encapsulating layer of silicone resin, which, together with the base substrate, bestows stiffness on the photomultiplier device, preventing warpage, and covers and protects the chips.

Abstract: A system for identifying a plurality of components of a vehicle that includes a plurality of non-volatile memories for storing identifiers associated with the plurality of vehicle components, a controller of the plurality of the vehicle components, a communication network configured for connecting the controller to the plurality of memories, and an identifiers memory including a portion to store a list of a plurality of type-approved identifiers associated with the plurality of type-approved vehicle components. The controller receives the identifiers, reads from the portion of the identifiers memory the list of type-approved identifiers, and checks if the identifiers of the plurality of components are included in the list of the type-approved identifiers, and when the controller detects that an identifier associated with a component out of the plurality of components is not included in the list, the controller blocks operation of the component.

Abstract: A process is described for integrating two closely spaced thin films without deposition of the films through deep vias. The films may be integrated on a wafer and patterned to form a microscale heat-trimmable resistor. A thin-film heating element may be formed proximal to a thin-film resistive element, and heat generated by the thin-film heater can be used to permanently trim a resistance value of the thin-film resistive element. Deposition of the thin films over steep or abrupt topography is minimized by using a process in which the thin films are deposited in a sequence that falls between depositions of thick metal contacts to the thin films.

Abstract: A method for carrying out nucleic acid amplification, includes providing a reaction chamber (31), accommodating an array (36) of nucleic acid probes (37) at respective locations, for hybridizing to respective target nucleic acids; and introducing a solution (50) into the reaction chamber (31), wherein the solution (50) contains primers, capable of binding to target nucleic acids, nucleotides, nucleic acid extending enzymes and a sample including nucleic acids. The a structure of the nucleic acid probes (37) and of the primers so that a hybridization temperature (TH) of the probes (37) is higher than an annealing temperature (TA) of the primers, whereby hybridization and annealing take place in respective separate temperature ranges (RH, RA).