Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

Abstract: A vertical conduction integrated electronic device including: a semiconductor body; a trench that extends through part of the semiconductor body and delimits a portion of the semiconductor body, which forms a first conduction region having a first type of conductivity and a body region having a second type of conductivity, which overlies the first conduction region; a gate region of conductive material, which extends within the trench; an insulation region of dielectric material, which extends within the trench and is arranged between the gate region and the body region; and a second conduction region, which overlies the body region. The second conduction region is formed by a conductor.

Abstract: A semiconductor substrate includes a first portion and a second portion. The first portion of the substrate has a first deformation-stress sensor capable of supplying a first stress signal. The second portion of the substrate has a second deformation-stress sensor capable of supplying a second stress signal. The first stress signal and second stress signal are processed by a circuit to produce a compensation signal. The compensation signal is applied in feedback to one of the first and second stress signals to compensate for variations induced in said one of the first and second stress signals by stresses in the semiconductor substrate.

Abstract: A voltage-current converter includes a first input stage and a second input stage with a first transistor and a second transistor driven by the first input stage and by the second input stage, respectively. First and second current generators are coupled to current lines of the first transistor and of the second transistor. At least one resistor couples the current lines of the first transistor and of the second transistor, where the ends of the aforesaid resistor are coupled to feedback terminals of the input stages so that an input voltage applied between voltage input terminals of the input stages is converted into a current on respective current output terminals of the converter. The converter includes switching circuits for coupling the first and second current generators alternately to the current line of the first transistor and to the current line of the second transistor.

Abstract: A testing system for carrying out electrical testing of at least one first through via forms an insulated via structure extending only part way through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the insulated via structure. The first electrical test circuit enables detection of at least one electrical parameter of the insulated via structure.

Abstract: A device of the Substitution-Box (S-Box) type, which is suitable for operating in a symmetric-key encryption apparatus, in particular an AES (Advanced Encryption Standard) encryption apparatus, and includes at least one module configured for carrying out a non-linear operation in a finite field (GF(28)) of an encryption method implemented by the above encryption apparatus, the module including at least one reprogrammable look-up table to, for example, implement countermeasures against side-channel attacks. When no countermeasures are employed, the tables may be set to fixed values, instead of being reprogrammable. The above module includes a plurality of composite look-up tables that implement the non-linear operation in a composite field of finite subfields (GF(24)2; GF((22)2)2) deriving from the finite field (GF(28)), each of the above composite look-up tables being smaller than a look-up table that is able to implement autonomously the non-linear operation in a finite field (GF(28)).

Abstract: A probe card includes a number probes. Each probe is adapted to contact a corresponding terminal of a circuit integrated in at least one die of a semiconductor material wafer during a test phase of the wafer. The probes include at least one probe adapted to provide and/or receive a radio frequency test signal to/from the corresponding terminal during the test phase. The probe card further includes at least one electromagnetic shield structure corresponding to the at least one probe adapted to provide and/or receive the radio frequency test signal for the at least partial shielding of an electromagnetic field irradiated by such at least one probe adapted to provide and/or receive the radio frequency test signal.

Abstract: An amplifier circuit, for a capacitive acoustic transducer defining a sensing capacitor that generates a sensing signal as a function of an acoustic signal, has a first input terminal and a second input terminal, which are coupled to the sensing capacitor and: a dummy capacitor, which has a capacitance corresponding to a capacitance at rest of the sensing capacitor and a first terminal connected to the first input terminal; a first buffer amplifier, which is coupled at input to the second input terminal and defines a first differential output of the circuit; a second buffer amplifier, which is coupled at input to a second terminal of the dummy capacitor and defines a second differential output of the circuit; and a feedback stage, which is coupled between the differential outputs and the first input terminal, for feeding back onto the first input terminal a feedback signal, which has an amplitude that is a function of the sensing signal and is in phase opposition with respect thereto.

Abstract: A microprocessor of a solid state memory protects the contents of the solid state memory by comparing a sequence of requests for access to physical blocks of the solid state memory with a predetermined sequence of requests to verify the sequence of requests, and by responding to additional requests for access to the physical blocks of the solid state memory to decrypt and transfer requested files stored therein when the sequence of requests equals the predetermined sequence of requests, thereby verifying the sequence of requests. The predetermined sequence of requests is associated with a plurality of virtual files that can be selected, in a particular sequence, to simulate a request for access to physical blocks of the solid state memory, while the predetermined sequence of requests is stored in a configuration file of the solid state memory in correspondence with an identifier of additional protected files.

Abstract: Embodiments of the present disclosure are directed to a microfluidic delivery system that includes a microfluidic semiconductor die coupled to a flexible interconnect substrate to form an assembly. At least one embodiment is directed to a semiconductor die having an active surface that includes a layout that has electrically active bond pads along one side of the active surface of the die. A second side of the active surface of the die includes one or more mechanical pads.

Abstract: A microelectromechanical gyroscope includes: a substrate; a stator sensing structure fixed to the substrate; a first mass elastically constrained to the substrate and movable with respect to the substrate in a first direction; a second mass elastically constrained to the first mass and movable with respect to the first mass in a second direction; and a third mass elastically constrained to the second mass and to the substrate and capacitively coupled to the stator sensing structure, the third mass being movable with respect to the substrate in the second direction and with respect to the second mass in the first direction.

Abstract: A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.

Abstract: LED strings cascaded to one another are driven by an electronic circuit that includes regulation modules and a brightness-compensation module. The regulation modules carry out in sequence a current-regulation phase, in which they regulate the current that flows in the corresponding LED strings. The regulation module includes: a compensation regulator coupled to a compensation LED string and to a capacitor and a generator that generates an electrical quantity indicating the luminous flux emitted by the LED strings and by the compensation LED string. The compensation regulator regulates a current that flows in the compensation LED string as a function of the electrical quantity, discharging the capacitor through the compensation LED string.

Abstract: A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal.

Abstract: A clock recovery circuit includes an oscillator to generate a clock signal. The oscillator varies a frequency of the clock signal as a function of a control signal. The clock recovery circuit has a phase tracking control loop to determine the phase error between the reference signal and the clock signal, and vary the control signal as a function of the phase error. The phase tracking control loop has a linear region for phase errors in the range between ?? and +?, thereby creating a cycle slippage event when the phase error exceed said range. The clock recovery circuit includes a cycle-slippage detector which determines whether the phase error reaches or approaches +? or ??. In case the phase error reaches or approaches +? or ??, the cycle-slippage detector acts on the control signal in an effort to avoid that said phase tracking control loop leaves said linear region.

Abstract: Described herein is a MEMS acoustic transducer device provided with a micromechanical detection structure that detects acoustic-pressure waves and supplies a transduced electrical quantity, and with an integrated circuit operatively coupled to the micromechanical detection structure and having a reading module that generates at output an audio signal as a function of the transduced electrical quantity. The integrated circuit is further provided with a recognition module, which recognizes a sound activity event associated to the transduced electrical quantity. The MEMS acoustic transducer has an output that supplies at output a data signal that carries information regarding recognition of the sound activity event.

Abstract: A reflector micromechanical structure includes a frame with a window. The frame is elastically connected to an anchorage structure by first elastic elements. An actuation structure operatively coupled to the frame is configured to generate a first actuation movement of the frame about a first actuation axis. A mobile mass is positioned within the window and elastically coupled to the frame by second elastic elements. A mass distribution is associated to the mobile mass such as to generate, by an inertial effect in response to the first actuation movement, a second actuation movement of rotation of the mobile mass about a second actuation axis.

Abstract: An integrated vacuum microelectronic structure is described as having a highly doped semiconductor substrate, a first insulating layer placed above said doped semiconductor substrate, a first conductive layer placed above said first insulating layer, a second insulating layer placed above said first conductive layer, a vacuum trench formed within said first and second insulating layers and extending to the highly doped semiconductor substrate, a second conductive layer placed above said vacuum trench and acting as a cathode, a third metal layer placed under said highly doped semiconductor substrate and acting as an anode, said second conductive layer is placed adjacent to the upper edge of said vacuum trench, the first conductive layer is separated from said vacuum trench by portions of said second insulating layer and is in electrical contact with said second conductive layer.

Abstract: An integrated circuit package with improved reliability and methods for creating the same are disclosed. More specifically, integrated circuit packages are created using one or more sacrificial layers that provide support for ink printed wires prior to package processing, but are removed during package processing. Once each of the sacrificial layers is removed, molding compound is placed around each ink printed wire, which may have a substantially rectangular cross section that can vary in dimension along a length of a given wire. While substantially surrounding each wire in and of itself improves reliability, removing non-conductive paste, fillets, or other adhesive materials also minimizes adhesion issues between the molding compound and those materials, which increases the bond of the molding compound to the package and its components. The net result is a more reliable integrated circuit package that is less susceptible to internal cracking and wire damage.

Abstract: A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled to the device substrate above the top face so as to cover the first integrated device in such a manner that a first empty space is provided above the membrane. Electrical-contact elements electrically connect the integrated device with the outside of the substrate-level assembly. In one embodiment, the device substrate integrates at least a further integrated device provided with a respective membrane, and a further empty space, fluidly isolated from the first empty space, is provided over the respective membrane of the further integrated device.