Patents Assigned to STMicroelectronics (Tours) SAS
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Patent number: 12261059Abstract: The present description concerns a method of manufacturing a device comprising at least one radio frequency component on a semiconductor substrate comprising: a) a laser anneal of a first thickness of the substrate on the upper surface side of the substrate; b) the forming of an insulating layer on the upper surface of the substrate; and c) the forming of said at least one radio frequency component on the insulating layer.Type: GrantFiled: August 3, 2022Date of Patent: March 25, 2025Assignee: STMICROELECTRONICS (TOURS) SASInventor: Patrick Hauttecoeur
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Patent number: 12230698Abstract: A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.Type: GrantFiled: February 15, 2023Date of Patent: February 18, 2025Assignee: STMicroelectronics (Tours) SASInventors: Patrick Hauttecoeur, Vincent Caro
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Patent number: 12230628Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.Type: GrantFiled: November 8, 2022Date of Patent: February 18, 2025Assignee: STMICROELECTRONICS (TOURS) SASInventor: Aurelie Arnaud
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Patent number: 12230602Abstract: A method for manufacturing electronic chips includes depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin. The method includes forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit. Metal connection pillars are formed by filling the cavities with metal. The integrated circuits are separated into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.Type: GrantFiled: July 8, 2022Date of Patent: February 18, 2025Assignee: STMICROELECTRONICS (TOURS) SASInventors: Ludovic Fallourd, Christophe Serre
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Patent number: 12184196Abstract: A converter includes first and second transistors coupled between first and second nodes, and first and second thyristors coupled between the first and second nodes. The converter is controlled for operation to: in first periods, turn the first transistor and second thyristor on and turn the second transistor and the first thyristor off, and in second periods, turn the first transistor and the second thyristor off and turn the second transistor and the first thyristor on. Further control of converter operation includes, for a third period following each first period, turning the first and second transistors off, turning the second thyristor off, and injecting a current into the gate of the first thyristor. Additional control of converter operation includes, for a fourth period following each second period, turning the first and second transistors off, turning the first thyristor off, and injecting a current into the gate of the second thyristor.Type: GrantFiled: September 6, 2022Date of Patent: December 31, 2024Assignee: STMicroelectronics (Tours) SASInventors: Yannick Hague, Romain Launois
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Patent number: 12101022Abstract: A voltage converter includes a circuit formed by a parallel association, connected between first and second nodes, of a first branch and a second branch. The first branch includes a first controlled rectifying element having a first impedance. The second branch includes a resistor associated in series with a second rectifying element having a second impedance substantially equal to the first impedance. The second rectifying element may, for example, be a triac having its gate coupled to receive a signal from an intermediate node in the series association of the second branch. Alternatively, the second rectifying element may be a thyristor having its gate coupled to receive a signal at the anode of the thyristor.Type: GrantFiled: December 14, 2021Date of Patent: September 24, 2024Assignee: STMicroelectronics (Tours) SASInventors: Yannick Hague, Benoit Renard, Romain Launois
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Patent number: 12095024Abstract: A thin-film lithium ion battery includes a negative electrode layer, a positive electrode layer, an electrolyte layer disposed between the positive and negative electrode layers, and a lithium layer with lithium pillars extending therefrom formed in the negative electrode layer adjoining the electrolyte layer.Type: GrantFiled: June 15, 2023Date of Patent: September 17, 2024Assignee: STMicroelectronics (Tours) SASInventors: Séverin Larfaillou, Delphine Guy-Bouyssou
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Publication number: 20240275298Abstract: Disclosed herein is a voltage converter including input nodes configured to receive an input voltage, output nodes configured to deliver an output voltage, a rectifying bridge coupled between the input nodes and the output nodes, a capacitor and a resistor series-coupled between the output nodes, and a thyristor coupled between one terminal of the resistor and a given one of the output nodes, wherein the thyristor is configured to allow flow of a positive current from the resistor to the given one of the output nodes. A control input is configured to receive a control signal, wherein the control signal biases a gate of the thyristor to control the flow of current through the thyristor. transient voltage suppressor circuit is coupled to the gate of the thyristor, configured to activate the thyristor upon exceeding a threshold voltage.Type: ApplicationFiled: April 23, 2024Publication date: August 15, 2024Applicant: STMicroelectronics (Tours) SASInventors: Yannick HAGUE, Romain LAUNOIS
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Publication number: 20240204112Abstract: A device includes a diode. The anode of the diode includes first, second, and third areas. The first area partially covers the second area and has a forst doping level greater than a second doping level of the second area. The second area partially covers the third area and has the second doping level greater than a third doping level of the third area. A first insulating layer partially overlaps the first and second areas.Type: ApplicationFiled: March 1, 2024Publication date: June 20, 2024Applicant: STMicroelectronics (Tours) SASInventors: Arnaud YVON, Lionel JAOUEN
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Publication number: 20240194666Abstract: Overvoltage protection circuits are provided. In some embodiments, an overvoltage protection circuit includes a first diode made of a first semiconductor material having a bandgap width greater than that of silicon. A second diode is included and is electrically cross-coupled with the first diode. The second diode is made of a second semiconductor material different from the first semiconductor material.Type: ApplicationFiled: February 16, 2024Publication date: June 13, 2024Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (TOURS) SASInventors: Jean-Michel SIMONNET, Sophie NGO, Simone RASCUNÀ
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Patent number: 12009658Abstract: The present disclosure relates to a transient voltage suppression device comprising a single crystal semiconductor substrate doped with a first conductivity type comprising first and second opposing surfaces, a semiconductor region doped with a second conductivity type opposite to the first conductivity type extending into the substrate from the first surface, a first electrically conductive electrode on the first side contacting the semiconductor region and a second electrically conductive electrode on the second side contacting the substrate, a first interface between the substrate and the semiconductor region forming the junction of a TVS diode and a second interface between the first electrically conductive electrode and the semiconductor region or between the substrate and the second electrically conductive electrode forming the junction of a Schottky diode.Type: GrantFiled: April 29, 2022Date of Patent: June 11, 2024Assignee: STMicroelectronics (Tours) SASInventors: Jean-Michel Simonnet, David Jouve, Frédéric Lanois
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Patent number: 11996784Abstract: A voltage converter delivers an output voltage between a first and a second node. The voltage converter includes a capacitor series-coupled with a resistor between the first and second nodes. The resistor is coupled in parallel with a bidirectional switch receiving at its control terminal a positive bias voltage referenced to the second node.Type: GrantFiled: November 22, 2021Date of Patent: May 28, 2024Assignee: STMicroelectronics (Tours) SASInventors: Yannick Hague, Romain Launois
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Publication number: 20240128311Abstract: The present disclosure relates to a capacitor including a first conductive layer over which is formed a stack, comprising from the upper face of the first layer, a first electrode, a first dielectric layer, a second electrode, and a second conductive layer, the stack comprising a stair step within the second conductive layer, the second electrode, and a part of the thickness of the first dielectric layer, the stair step being filled with a second dielectric layer so that the sidewalls of the first electrode are aligned with respect to the sidewalls of the second dielectric layer.Type: ApplicationFiled: July 24, 2023Publication date: April 18, 2024Applicant: STMICROELECTRONICS (TOURS) SASInventor: Mohamed BOUFNICHEL
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Patent number: 11955480Abstract: The present disclosure concerns an integrated circuit comprising a substrate, the substrate comprising a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the circuit comprising a three-dimensional capacitor formed inside and on top of the first region, and at least first and second connection terminals formed on the second region, the first and second connection terminals being respectively connected to first and second electrodes of the three-dimensional capacitor.Type: GrantFiled: May 11, 2022Date of Patent: April 9, 2024Assignee: STMICROELECTRONICS (TOURS) SASInventor: Mohamed Boufnichel
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Publication number: 20240113704Abstract: A method for controlling a MOS transistor compares a first voltage between a drain and a source of the MOS transistor to a second controllable threshold voltage. When the first voltage is smaller than a third voltage, a fourth control voltage is applied to the MOS transistor that is greater than a fifth threshold voltage of the MOS transistor. When the first voltage is greater than the second voltage, the fourth control voltage applied to the MOS transistor is smaller than the fifth voltage. The second voltage is equal to a first constant value between a first time and a second time, and is equal to a second variable value between the second time and a third time. The second value is equal to a sum of the first voltage and a sixth positive voltage. The third time corresponds to a time when the first voltage inverts.Type: ApplicationFiled: September 22, 2023Publication date: April 4, 2024Applicant: STMicroelectronics (Tours) SASInventors: Diawoye CISSE, Bertrand RIVET, Frederic GAUTIER
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Patent number: 11949023Abstract: A device includes a diode. The anode of the diode includes first, second, and third areas. The first area partially covers the second area and has a first doping level greater than a second doping level of the second area. The second area partially covers the third area and has the second doping level greater than a third doping level of the third area. A first insulating layer partially overlaps the first and second areas.Type: GrantFiled: December 20, 2021Date of Patent: April 2, 2024Assignee: STMicroelectronics (Tours) SASInventors: Arnaud Yvon, Lionel Jaouen
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Patent number: 11936288Abstract: An AC capacitor is coupled to a totem-pole type PFC circuit. In response to detection of a power input disconnection, the PFC circuit is controlled to discharge the AC capacitor. The PFC circuit includes a resistor and a first MOSFET and a second MOSFET coupled in series between DC output nodes with a common node coupled to the AC capacitor. When the disconnection event is detected, one of the first and second MOSFETs is turned on to discharge the AC capacitor with a current flowing through the resistor and the turned on MOSFET. Furthermore, a thyristor may be simultaneously turned on, with the discharge current flowing through a series coupling of the MOSFET, resistor and thyristor. Disconnection is detected by detecting a zero-crossing failure of an AC power input voltage or lack of input voltage decrease or input current increase in response to MOSFET turn on for a DC input.Type: GrantFiled: December 13, 2021Date of Patent: March 19, 2024Assignees: STMicroelectronics (Tours) SAS, STMicroelectronics LTDInventors: Ghafour Benabdelaziz, Laurent Gonthier
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Patent number: 11935884Abstract: Overvoltage protection circuits are provided. In some embodiments, an overvoltage protection circuit includes a first diode made of a first semiconductor material having a bandgap width greater than that of silicon. A second diode is included and is electrically cross-coupled with the first diode. The second diode is made of a second semiconductor material different from the first semiconductor material.Type: GrantFiled: November 30, 2022Date of Patent: March 19, 2024Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (TOURS) SASInventors: Jean-Michel Simonnet, Sophie Ngo, Simone Rascuna'
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Publication number: 20240088885Abstract: A control circuit for controlling a first transistor includes a diode for suppressing transient voltages. A cathode of the diode is coupled to a first conduction terminal of the first transistor, and an anode of the diode is coupled to a first node. A first resistor is coupled between the first node and a control terminal of the first transistor. A second transistor has a control terminal coupled to the first node, a first conduction terminal configured to receive a first supply voltage, and a second conduction terminal coupled to the control terminal of the first transistor.Type: ApplicationFiled: September 20, 2023Publication date: March 14, 2024Applicant: STMicroelectronics (Tours) SASInventors: Jean-Michel SIMONNET, Fabrice GUITTON
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Patent number: 11923234Abstract: The present disclosure relates to a method for manufacturing electronic chips. The method includes forming a plurality of trenches on a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed. The trenches delimit laterally a plurality of chips, and each of the chips includes a single integrated circuit. The method further includes electrically isolating flanks of each of the chips by forming an electrically isolating layer on lateral walls of the trenches.Type: GrantFiled: November 17, 2020Date of Patent: March 5, 2024Assignee: STMicroelectronics (Tours) SASInventor: Ludovic Fallourd