Patents Assigned to STMicroelectronics (Tours) SAS
  • Patent number: 12261059
    Abstract: The present description concerns a method of manufacturing a device comprising at least one radio frequency component on a semiconductor substrate comprising: a) a laser anneal of a first thickness of the substrate on the upper surface side of the substrate; b) the forming of an insulating layer on the upper surface of the substrate; and c) the forming of said at least one radio frequency component on the insulating layer.
    Type: Grant
    Filed: August 3, 2022
    Date of Patent: March 25, 2025
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventor: Patrick Hauttecoeur
  • Patent number: 12230698
    Abstract: A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: February 18, 2025
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Patrick Hauttecoeur, Vincent Caro
  • Patent number: 12230628
    Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: February 18, 2025
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventor: Aurelie Arnaud
  • Patent number: 12230602
    Abstract: A method for manufacturing electronic chips includes depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin. The method includes forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit. Metal connection pillars are formed by filling the cavities with metal. The integrated circuits are separated into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: February 18, 2025
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventors: Ludovic Fallourd, Christophe Serre
  • Patent number: 12184196
    Abstract: A converter includes first and second transistors coupled between first and second nodes, and first and second thyristors coupled between the first and second nodes. The converter is controlled for operation to: in first periods, turn the first transistor and second thyristor on and turn the second transistor and the first thyristor off, and in second periods, turn the first transistor and the second thyristor off and turn the second transistor and the first thyristor on. Further control of converter operation includes, for a third period following each first period, turning the first and second transistors off, turning the second thyristor off, and injecting a current into the gate of the first thyristor. Additional control of converter operation includes, for a fourth period following each second period, turning the first and second transistors off, turning the first thyristor off, and injecting a current into the gate of the second thyristor.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: December 31, 2024
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Yannick Hague, Romain Launois
  • Patent number: 12101022
    Abstract: A voltage converter includes a circuit formed by a parallel association, connected between first and second nodes, of a first branch and a second branch. The first branch includes a first controlled rectifying element having a first impedance. The second branch includes a resistor associated in series with a second rectifying element having a second impedance substantially equal to the first impedance. The second rectifying element may, for example, be a triac having its gate coupled to receive a signal from an intermediate node in the series association of the second branch. Alternatively, the second rectifying element may be a thyristor having its gate coupled to receive a signal at the anode of the thyristor.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: September 24, 2024
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Yannick Hague, Benoit Renard, Romain Launois
  • Patent number: 12095024
    Abstract: A thin-film lithium ion battery includes a negative electrode layer, a positive electrode layer, an electrolyte layer disposed between the positive and negative electrode layers, and a lithium layer with lithium pillars extending therefrom formed in the negative electrode layer adjoining the electrolyte layer.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: September 17, 2024
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Séverin Larfaillou, Delphine Guy-Bouyssou
  • Publication number: 20240275298
    Abstract: Disclosed herein is a voltage converter including input nodes configured to receive an input voltage, output nodes configured to deliver an output voltage, a rectifying bridge coupled between the input nodes and the output nodes, a capacitor and a resistor series-coupled between the output nodes, and a thyristor coupled between one terminal of the resistor and a given one of the output nodes, wherein the thyristor is configured to allow flow of a positive current from the resistor to the given one of the output nodes. A control input is configured to receive a control signal, wherein the control signal biases a gate of the thyristor to control the flow of current through the thyristor. transient voltage suppressor circuit is coupled to the gate of the thyristor, configured to activate the thyristor upon exceeding a threshold voltage.
    Type: Application
    Filed: April 23, 2024
    Publication date: August 15, 2024
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Yannick HAGUE, Romain LAUNOIS
  • Publication number: 20240204112
    Abstract: A device includes a diode. The anode of the diode includes first, second, and third areas. The first area partially covers the second area and has a forst doping level greater than a second doping level of the second area. The second area partially covers the third area and has the second doping level greater than a third doping level of the third area. A first insulating layer partially overlaps the first and second areas.
    Type: Application
    Filed: March 1, 2024
    Publication date: June 20, 2024
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Arnaud YVON, Lionel JAOUEN
  • Publication number: 20240194666
    Abstract: Overvoltage protection circuits are provided. In some embodiments, an overvoltage protection circuit includes a first diode made of a first semiconductor material having a bandgap width greater than that of silicon. A second diode is included and is electrically cross-coupled with the first diode. The second diode is made of a second semiconductor material different from the first semiconductor material.
    Type: Application
    Filed: February 16, 2024
    Publication date: June 13, 2024
    Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (TOURS) SAS
    Inventors: Jean-Michel SIMONNET, Sophie NGO, Simone RASCUNÀ
  • Patent number: 12009658
    Abstract: The present disclosure relates to a transient voltage suppression device comprising a single crystal semiconductor substrate doped with a first conductivity type comprising first and second opposing surfaces, a semiconductor region doped with a second conductivity type opposite to the first conductivity type extending into the substrate from the first surface, a first electrically conductive electrode on the first side contacting the semiconductor region and a second electrically conductive electrode on the second side contacting the substrate, a first interface between the substrate and the semiconductor region forming the junction of a TVS diode and a second interface between the first electrically conductive electrode and the semiconductor region or between the substrate and the second electrically conductive electrode forming the junction of a Schottky diode.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: June 11, 2024
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Jean-Michel Simonnet, David Jouve, Frédéric Lanois
  • Patent number: 11996784
    Abstract: A voltage converter delivers an output voltage between a first and a second node. The voltage converter includes a capacitor series-coupled with a resistor between the first and second nodes. The resistor is coupled in parallel with a bidirectional switch receiving at its control terminal a positive bias voltage referenced to the second node.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: May 28, 2024
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Yannick Hague, Romain Launois
  • Publication number: 20240128311
    Abstract: The present disclosure relates to a capacitor including a first conductive layer over which is formed a stack, comprising from the upper face of the first layer, a first electrode, a first dielectric layer, a second electrode, and a second conductive layer, the stack comprising a stair step within the second conductive layer, the second electrode, and a part of the thickness of the first dielectric layer, the stair step being filled with a second dielectric layer so that the sidewalls of the first electrode are aligned with respect to the sidewalls of the second dielectric layer.
    Type: Application
    Filed: July 24, 2023
    Publication date: April 18, 2024
    Applicant: STMICROELECTRONICS (TOURS) SAS
    Inventor: Mohamed BOUFNICHEL
  • Patent number: 11955480
    Abstract: The present disclosure concerns an integrated circuit comprising a substrate, the substrate comprising a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the circuit comprising a three-dimensional capacitor formed inside and on top of the first region, and at least first and second connection terminals formed on the second region, the first and second connection terminals being respectively connected to first and second electrodes of the three-dimensional capacitor.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: April 9, 2024
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventor: Mohamed Boufnichel
  • Publication number: 20240113704
    Abstract: A method for controlling a MOS transistor compares a first voltage between a drain and a source of the MOS transistor to a second controllable threshold voltage. When the first voltage is smaller than a third voltage, a fourth control voltage is applied to the MOS transistor that is greater than a fifth threshold voltage of the MOS transistor. When the first voltage is greater than the second voltage, the fourth control voltage applied to the MOS transistor is smaller than the fifth voltage. The second voltage is equal to a first constant value between a first time and a second time, and is equal to a second variable value between the second time and a third time. The second value is equal to a sum of the first voltage and a sixth positive voltage. The third time corresponds to a time when the first voltage inverts.
    Type: Application
    Filed: September 22, 2023
    Publication date: April 4, 2024
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Diawoye CISSE, Bertrand RIVET, Frederic GAUTIER
  • Patent number: 11949023
    Abstract: A device includes a diode. The anode of the diode includes first, second, and third areas. The first area partially covers the second area and has a first doping level greater than a second doping level of the second area. The second area partially covers the third area and has the second doping level greater than a third doping level of the third area. A first insulating layer partially overlaps the first and second areas.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: April 2, 2024
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Arnaud Yvon, Lionel Jaouen
  • Patent number: 11936288
    Abstract: An AC capacitor is coupled to a totem-pole type PFC circuit. In response to detection of a power input disconnection, the PFC circuit is controlled to discharge the AC capacitor. The PFC circuit includes a resistor and a first MOSFET and a second MOSFET coupled in series between DC output nodes with a common node coupled to the AC capacitor. When the disconnection event is detected, one of the first and second MOSFETs is turned on to discharge the AC capacitor with a current flowing through the resistor and the turned on MOSFET. Furthermore, a thyristor may be simultaneously turned on, with the discharge current flowing through a series coupling of the MOSFET, resistor and thyristor. Disconnection is detected by detecting a zero-crossing failure of an AC power input voltage or lack of input voltage decrease or input current increase in response to MOSFET turn on for a DC input.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: March 19, 2024
    Assignees: STMicroelectronics (Tours) SAS, STMicroelectronics LTD
    Inventors: Ghafour Benabdelaziz, Laurent Gonthier
  • Patent number: 11935884
    Abstract: Overvoltage protection circuits are provided. In some embodiments, an overvoltage protection circuit includes a first diode made of a first semiconductor material having a bandgap width greater than that of silicon. A second diode is included and is electrically cross-coupled with the first diode. The second diode is made of a second semiconductor material different from the first semiconductor material.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: March 19, 2024
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (TOURS) SAS
    Inventors: Jean-Michel Simonnet, Sophie Ngo, Simone Rascuna'
  • Publication number: 20240088885
    Abstract: A control circuit for controlling a first transistor includes a diode for suppressing transient voltages. A cathode of the diode is coupled to a first conduction terminal of the first transistor, and an anode of the diode is coupled to a first node. A first resistor is coupled between the first node and a control terminal of the first transistor. A second transistor has a control terminal coupled to the first node, a first conduction terminal configured to receive a first supply voltage, and a second conduction terminal coupled to the control terminal of the first transistor.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 14, 2024
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Jean-Michel SIMONNET, Fabrice GUITTON
  • Patent number: 11923234
    Abstract: The present disclosure relates to a method for manufacturing electronic chips. The method includes forming a plurality of trenches on a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed. The trenches delimit laterally a plurality of chips, and each of the chips includes a single integrated circuit. The method further includes electrically isolating flanks of each of the chips by forming an electrically isolating layer on lateral walls of the trenches.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: March 5, 2024
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Ludovic Fallourd