Patents Assigned to STMicroelectronics (Tours) SAS
-
Patent number: 11811395Abstract: A control device includes a triac and a first diode that is series-connected between the triac and a first terminal of the device that is configured to be connected to a cathode gate of a thyristor. A second terminal of the control device is configured to be connected to an anode of the thyristor. The triac has a gate connected to a third terminal of the device that is configured to receive a control signal. The thyristor is a component part of one or more of a rectifying bridge circuit, an in-rush current limiting circuit or a solid-state relay circuit.Type: GrantFiled: September 3, 2021Date of Patent: November 7, 2023Assignee: STMicroelectronics (Tours) SASInventors: Romain Pichon, Yannick Hague
-
Patent number: 11784104Abstract: The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.Type: GrantFiled: September 30, 2021Date of Patent: October 10, 2023Assignee: STMICROELECTRONICS (TOURS) SASInventors: Olivier Ory, Romain Jaillet
-
Publication number: 20230290770Abstract: An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.Type: ApplicationFiled: November 2, 2022Publication date: September 14, 2023Applicants: STMicroelectronics (Tours) SAS, STMicroelectronics S.r.l.Inventors: Aurelie Arnaud, Andrea Brischetto
-
Publication number: 20230275526Abstract: A rectifying element includes a MOS transistor series-connected with a Schottky diode. A bias voltage is applied between the control terminal of the MOS transistor and the terminal of the Schottky diode opposite to the transistor. A pair of the rectifying elements are substituted for diodes of a rectifying bridge circuit. Alternatively, the control terminal bias is supplied from a cross-coupling against the Schottky diodes. In another implementation, the Schottky diodes are omitted and the bias voltage applied to control terminals of the MOS transistors is switched in response to cross-coupled divided source-drain voltages of the MOS transistors. The circuits form components of a power converter.Type: ApplicationFiled: May 8, 2023Publication date: August 31, 2023Applicant: STMicroelectronics (Tours) SASInventor: Frederic GAUTIER
-
Patent number: 11721830Abstract: A thin-film lithium ion battery includes a negative electrode layer, a positive electrode layer, an electrolyte layer disposed between the positive and negative electrode layers, and a lithium layer with lithium pillars extending therefrom formed in the negative electrode layer adjoining the electrolyte layer.Type: GrantFiled: October 23, 2017Date of Patent: August 8, 2023Assignee: STMicroelectronics (Tours) SASInventors: Severin Larfaillou, Delphine Guy-Bouyssou
-
Publication number: 20230230906Abstract: The present disclosure concerns a method of manufacturing an electronic component and the obtained component, comprising a substrate, comprising the successive steps of: depositing a first layer of a first resin activated by abrasion to become electrically conductive, on a first surface of said substrate comprising at least one electric contact and, at least partially, on the lateral flanks of said substrate; partially abrading said first layer on the flanks of said substrate.Type: ApplicationFiled: January 13, 2023Publication date: July 20, 2023Applicant: STMICROELECTRONICS (TOURS) SASInventors: Nicolas MODE, Ludovic FALLOURD, Laurent BARREAU
-
Patent number: 11705827Abstract: A circuit includes two input nodes and two output nodes. A rectifier bridge is coupled to the input and output nodes. The rectifier bridge includes a first and second thyristors and a third thyristor coupled in series with a resistor in series. The series coupled third thyristor and resistor are coupled in parallel with one of the first and second thyristors. The first and second thyristors are controlled off, with the third thyristor controlled on, during start up with resistor functioning as an in in-rush current limiter circuit. In normal rectifying operation mode, the first and second thyristors are controlled on, with the third thyristor controlled off.Type: GrantFiled: August 16, 2022Date of Patent: July 18, 2023Assignee: STMicroelectronics (Tours) SASInventors: Yannick Hague, Romain Launois
-
Publication number: 20230215733Abstract: The present description concerns a method of forming a cavity in a substrate comprising: the forming of an etch mask comprising, opposite the location of the cavity, a plurality of sets of openings, the ratio between the openings and the mask of each set being selected according to the desired profile of the cavity opposite the surface of the mask having the set inscribed therein; and the wet etching of the substrate through the openings.Type: ApplicationFiled: December 29, 2022Publication date: July 6, 2023Applicant: STMICROELECTRONICS (TOURS) SASInventor: Mohamed BOUFNICHEL
-
Publication number: 20230198559Abstract: A circuit device includes a directional coupler with a first port receiving a radiofrequency signal, a second port outputting a signal in response to signal received by the first port, and a third port outputting a signal in response to a reflection of the signal at the second port. An impedance matching network is connected between the second port and an antenna. The impedance matching network includes fixed inductive and capacitive components and a single variable inductive or capacitive component. A diode coupled to the third port of the coupler generates a voltage at a measurement terminal which is processed in order to select and set the inductance or capacitance value of the variable inductive or capacitive component.Type: ApplicationFiled: February 24, 2023Publication date: June 22, 2023Applicant: STMicroelectronics (Tours) SASInventors: Jean Pierre PROOT, Pascal PAILLET, Francois DUPONT
-
Publication number: 20230197835Abstract: A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.Type: ApplicationFiled: February 15, 2023Publication date: June 22, 2023Applicant: STMicroelectronics (Tours) SASInventors: Patrick HAUTTECOEUR, Vincent CARO
-
Patent number: 11682981Abstract: A rectifying element includes a MOS transistor series-connected with a Schottky diode. A bias voltage is applied between the control terminal of the MOS transistor and the terminal of the Schottky diode opposite to the transistor. A pair of the rectifying elements are substituted for diodes of a rectifying bridge circuit. Alternatively, the control terminal bias is supplied from a cross-coupling against the Schottky diodes. In another implementation, the Schottky diodes are omitted and the bias voltage applied to control terminals of the MOS transistors is switched in response to cross-coupled divided source-drain voltages of the MOS transistors. The circuits form components of a power converter.Type: GrantFiled: February 18, 2020Date of Patent: June 20, 2023Assignee: STMicroelectronics (Tours) SASInventor: Frederic Gautier
-
Publication number: 20230187118Abstract: An integrated circuit device includes at least one inductive component with at least one integrated metal winding that is at least partially embedded in a coating. The coating includes at least one ferromagnetic material. The coating optionally includes a non-magnetic material, for example a dielectric.Type: ApplicationFiled: December 5, 2022Publication date: June 15, 2023Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Tours) SASInventors: Ludovic FOURNEAUD, Laurent MOINDRON, Gregory BOUTELOUP
-
Patent number: 11677236Abstract: A device for discharging a capacitor includes a resistive component having a resistance value selectable from among at least three resistance values. The device is configured to be connected in parallel with the capacitor. A circuit operates to select the resistance value of the resistive component.Type: GrantFiled: March 10, 2021Date of Patent: June 13, 2023Assignee: STMicroelectronics (Tours) SASInventor: Eric Colleoni
-
Publication number: 20230178380Abstract: A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.Type: ApplicationFiled: January 12, 2023Publication date: June 8, 2023Applicant: STMICROELECTRONICS (TOURS) SASInventors: Michael DE CRUZ, Olivier ORY
-
Patent number: 11664367Abstract: A protection device includes a first inductive element connecting first and second terminals and a second inductive element connecting third and fourth terminals. A first component includes a first avalanche diode connected in parallel with a first diode string, anodes of the first avalanche diode and a last diode in the string being connected to ground, cathodes of the first avalanche diode and a first diode in the string being connected, and a tap of the first diode string being connected to the first terminal. A second protection component includes a second avalanche diode connected in parallel with a second diode string, anodes of the second avalanche diode and a last diode in the string being connected to ground, cathodes of the second avalanche diode and a first diode in the string being connected, and a tap of the second diode string being connected to the third terminal.Type: GrantFiled: April 11, 2022Date of Patent: May 30, 2023Assignee: STMicroelectronics (Tours) SASInventor: Patrick Poveda
-
Publication number: 20230108617Abstract: Overvoltage protection circuits are provided. In some embodiments, an overvoltage protection circuit includes a first diode made of a first semiconductor material having a bandgap width greater than that of silicon. A second diode is included and is electrically cross-coupled with the first diode. The second diode is made of a second semiconductor material different from the first semiconductor material.Type: ApplicationFiled: November 30, 2022Publication date: April 6, 2023Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (TOURS) SASInventors: Jean-Michel SIMONNET, Sophie NGO, Simone RASCUNA'
-
Publication number: 20230104920Abstract: The present description concerns a device comprising at least one chip in a package, the package comprising a support, having the at least one chip resting thereon, and a protection layer covering the at least one chip, the support comprising a stack of layers made of an insulating material, a transformer being formed in the support by first and second conductive tracks.Type: ApplicationFiled: September 19, 2022Publication date: April 6, 2023Applicant: STMICROELECTRONICS (TOURS) SASInventors: Laurent MOINDRON, Ghafour BENABDELAZIZ
-
Patent number: 11621734Abstract: A circuit device includes a directional coupler with a first port receiving a radiofrequency signal, a second port outputting a signal in response to signal received by the first port, and a third port outputting a signal in response to a reflection of the signal at the second port. An impedance matching network is connected between the second port and an antenna. The impedance matching network includes fixed inductive and capacitive components and a single variable inductive or capacitive component. A diode coupled to the third port of the coupler generates a voltage at a measurement terminal which is processed in order to select and set the inductance or capacitance value of the variable inductive or capacitive component.Type: GrantFiled: May 17, 2021Date of Patent: April 4, 2023Assignee: STMicroelectronics (Tours) SASInventors: Jean Pierre Proot, Pascal Paillet, Francois Dupont
-
Publication number: 20230089468Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.Type: ApplicationFiled: November 8, 2022Publication date: March 23, 2023Applicant: STMICROELECTRONICS (TOURS) SASInventor: Aurelie ARNAUD
-
Patent number: 11610988Abstract: A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.Type: GrantFiled: March 1, 2021Date of Patent: March 21, 2023Assignee: STMicroelectronics (Tours) SASInventors: Patrick Hauttecoeur, Vincent Caro