Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.

Abstract: A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package.

Abstract: An electronic device includes a voltage divider producing different reference voltages. Dummy pixels each are formed by a transfer gate transistor having a first conduction terminal coupled to a floating diffusion node, a second conduction terminal, and a control node coupled to a first gate signal line, a transmission gate coupled between one of the plurality of taps and the second conduction terminal of the transfer gate transistor, a floating diffusion capacitor coupled between the floating diffusion node and ground, a transistor having a first conduction terminal coupled to the floating diffusion node, a second conduction terminal, and a control terminal coupled to a second gate signal line, and a reset transistor having a first conduction terminal coupled to the upper reference voltage, a second conduction terminal coupled to the second conduction terminal of the transistor, and a control terminal coupled to a reset signal line.

Abstract: A circuit includes an input port receiving an input signal having a first frequency. A phase-shifter network is coupled to the input port, receives the input signal, and produces therefrom first and second signals in quadrature with one another. Frequency multiplier circuitry has a common node and includes a first rectifier for rectifying the first signal to produce a first rectified signal having a second frequency that is twice the first frequency and to be applied to the common node, and a second rectifier rectifying the second signal to produce a second rectified signal having the second frequency and to be applied to the common node. A combination of the first and second rectified signals is available at the common node and includes harmonic contents at a frequency that is fourfold the first frequency.

Abstract: A control system for a laser scanning projector includes a mirror controller generating horizontal and vertical mirror synchronization signals for an oscillating mirror apparatus based upon a mirror clock signal, and laser modulation circuitry. The laser modulation circuitry generates horizontal and vertical laser synchronization signals as a function of a received laser clock signal, and generates control signals for a laser that emits a laser beam that impinges on the oscillating mirror apparatus. Synchronization circuitry generates the laser clock signal and sends the laser clock signal to the laser modulation circuitry, receives the horizontal and vertical mirror synchronization signals from the mirror controller, receives the horizontal and vertical laser synchronization signals from the laser modulation circuitry, and modifies the laser clock signal so as to achieve alignment between the horizontal and vertical mirror synchronization signals and the horizontal and vertical laser synchronization signals.

Abstract: A glitch detector includes an input flip-flop clocked by a clock signal and having a non-inverting data output, an inverting data output, and a data input receiving input from the inverting data output, the input flip-flop generating a divided version of the clock signal at the non-inverting data output. A configurable delay chain receives the divided version of the clock signal and generates a delayed version of the divided version of the clock signal as a delay output. An intermediate flip-flop clocked by the clock signal has a data input receiving the delay output, the intermediate flip-flop generating an intermediate output as a function of the delay output. A logic circuit receives the divided version of the clock signal and the intermediate output, and generates a glitch detect signal by performing a logical operation on the divided version of the clock signal and the intermediate output.

Abstract: An electronic converter has first and second input terminals, first and second output terminals, a current regulator circuit arranged between the first input terminal and an intermediate node, and input capacitor arranged between the intermediate node and the second input terminal, and an output capacitor. A control circuit block is configured to sense an input voltage, compare the regulated voltage to a reference value and generate a first signal, compare the input voltage to a lower threshold and an upper threshold and generate a second signal, switch the electronic converter between an active mode and an idle mode as a function of the first signal, and switch the electronic converter between a recharge phase and a switching phase as a function of the second signal when the electronic converter is in the active mode.

Abstract: A thyristor or triac control circuit includes a first capacitive element that is series-connected with a first diode between a first terminal and a second terminal intended to be coupled to a gate of the thyristor or triac. A second capacitive element is coupled between the second terminal and a third terminal intended to be connected to a conduction terminal of the thyristor or triac on the gate side of the thyristor or triac. A second diode is coupled between the third terminal and a node of connection of the first capacitive element and first diode.

Abstract: A microelectromechanical device includes a fixed structure defining a cavity with a tiltable structure that is elastically suspended in the cavity. A piezoelectrically driven actuation structure, interposed between the tiltable structure and the fixed structure, is biased for causing rotation of the tiltable structure about a first rotation axis belonging to a horizontal plane in which the tiltable structure rests. The actuation structure includes a pair of driving arms carry respective regions of piezoelectric material and are elastically coupled to the tiltable structure on opposite sides of the first rotation axis through respective elastic decoupling elements. The elastic decoupling elements exhibit stiffness in regard to movements out of the horizontal plane and compliance to torsion about the first rotation axis.

Abstract: A touch screen controller includes an input stage configured to receive and condition a touch output from a touch matrix to produce a touch signal. An accumulation stage is configured to receive the touch signal and accumulate the touch signal to produce an accumulated output. The accumulated output is digitized by an analog to digital converter to produce a touch strength value. A given amount of charge is subtracted from or added to accumulated output during a next accumulation if the touch strength value is greater than an upper threshold or less than a lower threshold. This avoids saturation of components in the touch screen controller and therefore increases the signal to noise ratio.

Abstract: A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor substrate via the rear face thereof is formed on and in the semiconductor wells. The device is a non-inverting buffer including an input terminal and an output terminal, the device being powered between a supply terminal and a reference terminal where the buried semiconductor layer provides the supply terminal. A control circuit delivers an input signal in a first state to the input terminal and outputs a control signal indicating a detection of a thinning of the substrate if a signal generated at the output terminal in response to the input signal is in a second state different from the first state.

Abstract: A MEMS device is obtained by forming a temporary biasing structure on a semiconductor body, and forming an actuation coil on the semiconductor body, the actuation coil having at least one first end turn, one second end turn and an intermediate turn arranged between the first and the second end turns and electrically coupled to the first end turn through the temporary biasing structure. In this way, the intermediate turn is biased at approximately the same potential as the first end turn during galvanic growth, and, at the end of growth, the actuation coil has an approximately uniform thickness. At the end of galvanic growth, portions of the temporary biasing structure are selectively removed to electrically separate the first end turn from the intermediate turn and from a dummy biasing region adjacent to the first end turn.

Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

Abstract: A digital representation of a waveform is generated based on signals received during a recording period. The received signals include a digital clock signal providing a determined number of clock pulses during the recording period, a plurality of binary digital signals defining, for each clock pulse of the determined number of clock pulses, a waveform state associated with the clock pulse. A digital representation of the waveform is generated and stored. The waveform has a duration based on the recording period and a profile based on the defined waveform states associated with the clock pulses of the determined number of clock pulses.

Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.

Abstract: A dual gate ion sensitive field effect transistor (ISFET) includes a first bias voltage node coupled to a back gate of the ISFET and a second bias voltage node coupled to a control gate of the ISFET. A bias voltage generator circuit is configured to generate a back gate voltage having a first magnitude and a first polarity for application to the first bias voltage node. The bias voltage generator circuit is further configured to generate a control gate voltage having a second magnitude and a second polarity for application to the second bias voltage node. The second polarity is opposite the first polarity.

Abstract: A method is provided for controlling the matching of an antenna to a transmission path. The transmission path includes an amplifier stage coupled at an input or at an output to the antenna and to a resistive load. The method includes performing a checking phase by measuring a first current temperature at or in proximity of the antenna and a second current temperature at or in proximity of the resistive load, triggering a matching of the impedance seen at the input or at the output of the amplifier stage in the presence of a first condition involving the first and second current temperatures, and then stopping the matching of the impedance in the presence of a second condition involving the second current temperature.

Abstract: A germanium waveguide is formed from a P-type silicon substrate that is coated with a heavily-doped N-type germanium layer and a first N-type doped silicon layer. Trenches are etched into the silicon substrate to form a stack of a substrate strip, a germanium strip, and a first silicon strip. This structure is then coated with a silicon nitride layer.

Abstract: An AC/DC converter includes a first terminal and a second terminal to receive an AC voltage and a third terminal and a fourth terminal to deliver a DC voltage. A rectifying bridge is provided in the converter. A controllable switching or rectifying element has a control terminal configured to receive a control current. A first switch is coupled between a supply voltage and the control terminal to inject the control current. A second switch is coupled between the control terminal and a reference voltage to extract the control current. The first and second switches are selectively actuated by a control circuit.