Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

Abstract: In a method of emulation of N boot programs in a memory, N being an integer greater than 2, the size of a no-access region of the memory containing the boot programs is increased in response to execution of each boot program.

Abstract: EEPROM emulation is provided in a phase-change memory of a circuit integrating a microprocessor. A granularity for writing into lines of the phase-change memory is defined according to a size of data packets to be written. A first error correction code calculated by a program executed by said microprocessor is associated with each data packet. Several data packets and their associated first error correction codes are then stored in a same line of the phase-change memory data packet.

Abstract: In providing electrical wire-like connections between at least one semiconductor die arranged on a semiconductor die mounting area of a substrate and an array of electrically-conductive leads in the substrate, pressure force is applied to the electrically-conductive leads in the substrate during bonding the wire-like connections to the electrically-conductive leads. Such a pressure force is applied to the electrically-conductive leads in the substrate via a pair of mutually co-operating force transmitting surfaces. These surfaces include a first convex surface engaging a second concave surface.

Abstract: An integrated circuit includes a plurality of flip-flops and a global reset network for resetting the flip-flops. The integrated circuit includes a synchronous clock delay circuit that delays, responsive to a global reset signal, a transition in a clock signal provided to the flip-flops. The delay in the transition of the clock signal ensures that all of the flip-flops receive the global reset signal within a same delayed clock cycle and that the flip-flops do not receive the global reset signal during a rising or falling edge of the clock signal.

Abstract: In an embodiment a method for detecting a presence of at least one object in a field of view of a time of flight sensor includes successively generating, by the time of flight sensor, histograms, each histogram comprising several classes associating a number of photons detected at a given acquisition period, adding several successively generated histograms so as to obtain a summed histogram and analyzing the summed histogram to detect the presence of at least one object in the field of view of the time of flight sensor.

Abstract: A process for manufacturing a MEMS piezoelectric device includes: forming a membrane at a first surface of wafer of semiconductor material further having a second surface (the first and second surfaces being opposite along a vertical axis and extending parallel to a horizontal plane formed by first and second horizontal axes); forming a cavity within the wafer so that the membrane is suspended above the cavity; forming a piezoelectric material layer above a first surface of the membrane; forming an electrode arrangement in contact with the piezoelectric material layer; and forming a proof mass coupled to a second surface of the membrane opposite to the first surface along the vertical axis. The proof mass deforms the membrane in response to environmental mechanical vibrations. Forming the proof mass includes forming a connection element at a central position between the membrane and the proof mass in the direction of the vertical axis.

Abstract: The present description concerns an electronic system including one or a plurality of first microprocessors, a second microprocessor for securely managing first encryption keys of the first microprocessors, the second microprocessor being configured to communicate with each first microprocessor and including a first non-volatile memory having at least one second key stored therein, and for each first microprocessor, a second non-volatile memory external to the second microprocessor and containing the first keys of the first microprocessor encrypted with the second key.

Abstract: A sensing pixel includes a single photon avalanche diode (SPAD) coupled between a first node and a second node, with a clamp diode being coupled between a turn-off voltage node and the second node. A turn-off circuit includes a sense circuit configured to generate a feedback voltage based upon a voltage at the turn-off voltage node, a transistor having a first conduction terminal coupled to the turn-off voltage node, a second conduction terminal coupled to ground, and a control terminal, and an amplifier having a first input coupled to a reference voltage, a second input coupled to receive the feedback voltage, and an output coupled to the control terminal of the transistor. A readout circuit is coupled to the SPAD by a decoupling capacitor.

Abstract: A semiconductor MOS device having an epitaxial layer with a first conductivity type formed by a drain region and by a drift region. The drift region accommodates a plurality of first columns with a second conductivity type and a plurality of second columns with the first conductivity type, the first and second columns alternating with each other and extending on the drain region. Insulated gate regions are each arranged on top of a respective second column; body regions having the second conductivity type extend above and at a distance from a respective first column, thus improving the output capacitance Cds of the device, for use in high efficiency RF applications.

Abstract: In an embodiment a non-volatile memory device includes a memory array having a plurality of memory cells, a control unit operatively coupled to the memory array, a biasing stage controllable by the control unit and configured to apply a biasing configuration to the memory cells to perform a memory operation and a reading stage coupled to the memory array and controllable by the control unit, the reading stage configured to verify whether the memory operation has been successful based on a verify level, wherein the control unit is configured to adaptively modify a value of the verify level based on an ageing of the memory cells.

Abstract: A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

Abstract: An analysis method of a device through a MEMS sensor is provided in which the MEMS sensor includes a control unit and a sensing assembly coupled to the device. The analysis method includes acquiring, through the sensing assembly, first data indicative of an operative state of the device. Testing is performed for the presence of a first abnormal operating condition of the device. If the first abnormal operating condition of the device is confirmed, a self-test of the sensing assembly is performed to generate a quantity indicative of an operative state of the sensing assembly. The self-test includes acquiring, through the sensing assembly, second data indicative of the operative state of the sensing assembly, generating a signature according to the second data, and processing the signature through deep learning techniques to generate said quantity.

Abstract: A thermographic sensor is proposed. The thermographic sensor includes a plurality of sensing elements each comprising at least one thermo-couple. The thermographic sensor is integrated on a semiconductor on insulator body that is patterned to define a grid suspended from a substrate; for each sensing element, the grid has a frame with the cold joint of the thermo-couple, a plate with the hot joint of the thermo-couple and one or more arms sustaining the plate from the frame. The frames include one or more conductive layers of thermally conductive material for thermally equalizing the cold joints with the substrate. Moreover, each sensing element may also include a processing circuit for the thermo-couple that is integrated on the corresponding frame. A thermographic device including the thermographic sensor and a corresponding signal processing circuit, and a system including one or more thermographic devices are also proposed.

Abstract: A embodiment method, for linearizing a transmission signal resulting from a quadrature amplitude modulation of an analog baseband signal and a radiofrequency amplification, comprises a demodulation of a feedback signal taken from the transmission signal, a comparison between the demodulated feedback signal and the baseband signal, a digital calculation of a predistortion control signal based on the comparison, and an analog predistortion of the analog baseband signal controlled by the predistortion control signal.

Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.

Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.

Abstract: The present disclosure is directed to a MOSFET device including a semiconductor body with: a plurality of source regions of a first conductivity type; a plurality of body regions of a second conductivity type, which form a plurality of channel regions; and a drain region of the first conductivity type. The MOSFET device further includes a plurality of insulated gate regions, each of which includes a respective gate conductive region and a respective gate dielectric region, which is partially interposed between the gate conductive region and corresponding source regions and is also partially interposed between the gate conductive region and corresponding channel regions. The MOSFET device further includes a plurality of barrier structures, each of which extends on a corresponding insulated gate region and includes at least one respective first barrier region of silicon nitride.

Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.