Patents Assigned to STMicroelectronics
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Publication number: 20240248864Abstract: A connection circuit couples a first circuit of a device to a bus configured to provide access to an addressable memory space of the device. The connection circuit receives an input address transmitted by the first circuit. The input address corresponds to an address in a first address range or a second address range of the addressable memory space. The addressable memory space further includes a third address range that is not addressable by the first circuit. The connection circuit compares the input address with a threshold address. In response to the comparison, the connection circuit generates a portion of an output address, the output address belonging to the second address range or the third address range of the addressable memory space. The portion of the output address is then supplied to the bus.Type: ApplicationFiled: January 18, 2024Publication date: July 25, 2024Applicant: STMicroelectronics International N.V.Inventors: Loic PALLARDY, Alexandre TORGUE
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Publication number: 20240250407Abstract: A near field communication (NFC) reader includes an NFC antenna and a wireless charging antenna. The NFC antenna substantially surrounds the wireless charging antenna laterally, except at an inward bend of the NFC antenna. The NFC antenna overlaps the wireless charging antenna at the bend.Type: ApplicationFiled: May 13, 2021Publication date: July 25, 2024Applicant: STMICROELECTRONICS (CHINA) INVESTMENT CO., LTD.Inventors: Tianhao XIONG, Chaolian LIANG
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Publication number: 20240249955Abstract: An multi-die semiconductor device disclosed herein includes a metallic leadframe with a central die pad encircled by electrically-conductive leads. Mounted on the die pad are two semiconductor dice, each with dedicated bonding pads on the surfaces facing away from the die pad. A layer of laser-activatable material is precisely molded over the dice and the leadframe. This layer forms a network of laser-activated lines: the first subset establishes electrical connections between the dice bonding pads and the leadframe leads, while the second subset interconnects the bonding pads of the first die to those of the second. There are two distinct metallic layers; the lower one, directly on the laser-activated lines, is formed of electroless-plated material, and the upper one, enhancing the structure, is formed of electroplated material, thus providing robust and reliable interconnections within the device.Type: ApplicationFiled: April 2, 2024Publication date: July 25, 2024Applicant: STMicroelectronics S.r.l.Inventor: Paolo CREMA
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Patent number: 12046324Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.Type: GrantFiled: July 11, 2022Date of Patent: July 23, 2024Assignees: STMicroelectronics International N.V., STMicroelectronics (Crolles 2) SASInventors: Harsh Rawat, Praveen Kumar Verma, Promod Kumar, Christophe Lecocq
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Patent number: 12045378Abstract: The present disclosure relates to a method for performing a cryptographic operation, the method including generating a first count value by a monotonic counter of a processing device, transmitting the first count value from the monotonic counter to a memory of the processing device, selecting a first encryption key from the memory based on the first count value, and providing the selected first encryption key to a cryptographic processor.Type: GrantFiled: March 30, 2022Date of Patent: July 23, 2024Assignees: STMicroelectronics (Grand Ouest) SAS, STMicroelectronics (Alps) SASInventors: Franck Albesa, Nicolas Anquet
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Patent number: 12046987Abstract: A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.Type: GrantFiled: January 24, 2022Date of Patent: July 23, 2024Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Laura Capecchi, Riccardo Zurla, Marcella Carissimi
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Patent number: 12048257Abstract: A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.Type: GrantFiled: April 5, 2023Date of Patent: July 23, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Jean-Philippe Reynard, Sylvie Del Medico, Philippe Brun
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Patent number: 12045336Abstract: An embedded electronic system includes a volatile memory and a processor configured to execute a low-level operating system that manages allocation of areas of the volatile memory to a plurality of high-level operating systems. Each high-level operating system executes one or more of applications. The volatile memory includes a first portion reserved for execution data of a first application and a second portion intended to store execution data of a second application. The system is configured so that once the execution data of the first application are loaded in the first portion, the low-level operating system forbids unloading of the execution data of the first application from the first portion so that the execution data of the first application remain in the volatile memory in case of a deactivation or of a setting to standby of the first application.Type: GrantFiled: September 20, 2021Date of Patent: July 23, 2024Assignees: STMicroelectronics S.r.l., Proton World International N.V.Inventors: Olivier Van Nieuwenhuyze, Amedeo Veneroso
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Patent number: 12044423Abstract: The present disclosure is directed to an air filter sensor system that can monitor a status of a filter and provide information to a remote system regarding the filter's status. The system can receive, by a computing server via one or more computer networks and from each of a plurality of sensor assemblies coupled to a corresponding plurality of air filters, information indicative of filter contamination levels respectively associated with each corresponding air filter of the plurality of air filters. Each of the respective filter contamination levels being provided by one sensor assembly of the plurality of sensor assemblies based at least in part on a difference in detected air pressure between first and second sides of the corresponding air filter.Type: GrantFiled: December 29, 2020Date of Patent: July 23, 2024Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS, INC.Inventors: Matteo Dameno, Mario Tesi, Marco Bianco, Mahesh Chowdhary, Michele Ferraina
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Patent number: 12048099Abstract: A base substrate has a thickness between two faces. The base substrate includes at least one hole extending in a thickness of the base substrate perpendicular to one of the two face. At least one dipole of a surface-mount device type is housed in the at least one hole of the base substrate.Type: GrantFiled: March 5, 2021Date of Patent: July 23, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventor: Pierino Calascibetta
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Patent number: 12045175Abstract: A system includes a processing unit, a memory configured to store at least one first group of instructions and one second group of instructions for execution by the processing unit, the processing unit being configured to sequentially extract from the memory instructions of the first group and instructions of the second group for their execution. The system also includes a controller including a first auxiliary memory configured to store a protection criterion, a comparator configured to compare the storage address of each extracted instruction with the protection criterion, and a control circuit configured to, in response to the storage address meeting the protection criterion, trigger a protection mechanism including at least one prohibition for the processing unit to execute again at least one portion of the instructions of the first group, during the execution of the instructions of the second group.Type: GrantFiled: December 3, 2021Date of Patent: July 23, 2024Assignee: STMicroelectronics (Grand Ouest) SASInventor: Frederic Ruelle
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Patent number: 12046655Abstract: A vertical conduction electronic power device includes a body delimited by a first and a second surface and having an epitaxial layer of semiconductor material, and a substrate. The epitaxial layer is delimited by the first surface of the body and the substrate is delimited by the second surface of the body. The epitaxial layer houses at least a first and a second conduction region having a first type of doping and a plurality of insulated-gate regions, which extend within the epitaxial layer. The substrate has at least one silicide region, which extends starting from the second surface of the body towards the epitaxial layer.Type: GrantFiled: January 28, 2021Date of Patent: July 23, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Davide Giuseppe Patti, Mario Giovanni Scurati, Marco Morelli
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Patent number: 12045377Abstract: The present disclosure relates to a method for decrypting encrypted data. The method includes generating a first count value by a monotonic counter of a processing device, deriving, using a key derivation circuit, a first encryption key based on the first count value, transmitting the first encryption key to a cryptographic processor; and decrypting, based on the first encryption key, first encrypted data.Type: GrantFiled: March 29, 2022Date of Patent: July 23, 2024Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grand Ouest) SASInventors: Franck Albesa, Nicolas Anquet
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Patent number: 12043540Abstract: This disclosure pertains to a microelectromechanical systems (MEMS) device with a tiltable structure, a fixed supporting structure, and an actuation structure with driving arms connected to the tiltable structure by elastic decoupling elements. Described herein, particularly, is a planar stop structure between the driving arms and the tiltable structure, which functions to limit movement in the tiltable plane. This stop structure includes a first projection/abutment surface pair formed by a projection extending from a driving arm and an abutment surface formed by a recess in the tiltable structure. The projection and abutment surface are adjacent and spaced apart in the device's rest condition.Type: GrantFiled: April 13, 2023Date of Patent: July 23, 2024Assignee: STMicroelectronics S.r.l.Inventors: Nicolo' Boni, Roberto Carminati, Massimiliano Merli
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Patent number: 12045339Abstract: In an embodiment a system on chip includes a persistent power supply and anti-replay mechanism comprising a monotonic counter including a volatile counter register powered by the persistent power supply.Type: GrantFiled: September 8, 2021Date of Patent: July 23, 2024Assignee: STMICROELECTRONICS S.R.L.Inventors: Antonino Mondello, Alessandro Inglese
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Patent number: 12047198Abstract: A device has a plurality of CAN XL communication systems, a bus, and a switching circuit. The bus has a transmission node and reception node, and receives from each CAN XL communication system a respective second transmission signal and drives the logic level at the transmission node as a function of the logic levels of the second transmission signals, and provides to each CAN XL communication system a respective second reception signal having a logic level determined as a function of the logic level at the reception node. The switching circuit supports a plurality of modes. In a first mode, the switching circuit is configured to provide the NRZ encoded transmission signals of the CAN XL communication systems as the second transmission signals to the bus system, and provide the respective second reception signal received from the bus to the CAN XL protocol controllers of the CAN XL communication system.Type: GrantFiled: May 19, 2023Date of Patent: July 23, 2024Assignee: STMICROELECTRONICS APPLICATION GMBHInventors: Fred Rennig, Rolf Nandlinger
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Publication number: 20240243698Abstract: An envelope detector receives a modulated signal and a differential stage coupled to the detector produces a replica modulated signal compared to produce a PWM-modulated signal having on and off times. A first switch is actuated to short-circuit the input to the envelope detector. A second switch is actuated to feed back to a storage capacitor a signal indicative of the difference between inputs to the differential stage. A third switch is actuated to short-circuit an input to the comparator. Logic circuitry activates the switched to implement offset compensation where: the first, second and third switches are actuated in the absence of the PWM-modulated signal during start-up and standby phases; and the first, second and third switches are actuated during off times of the PWM-modulated signal in a working phase alternating with the start-up/standby phases.Type: ApplicationFiled: January 10, 2024Publication date: July 18, 2024Applicant: STMicroelectronics International N.V.Inventors: Nunzio SPINA, Alessandro CASTORINA, Giuseppe PALMISANO
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Publication number: 20240243122Abstract: An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.Type: ApplicationFiled: January 18, 2024Publication date: July 18, 2024Applicant: STMICROELECTRONICS S.R.L.Inventors: Mario Giuseppe SAGGIO, Simone RASCUNÁ
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Publication number: 20240242749Abstract: A reset pad circuit has first and second inputs coupled, respectively, to a first reset access port receiving a first reset request and a second reset access port. The reset pad circuit generates a first reset state signal. An internal reset activation gate has inputs coupled to internal resources and an output that applies a reset request to the second reset access port. A memory element has first and second inputs coupled, respectively, to the output of the reset activation gate and the output of the reset pad circuit. The memory element generates a second reset state signal when receiving the reset request until receiving the first reset state signal. A reset forward gate coupled to outputs of the reset pad circuit and the memory element generates a system reset request in response to the first reset state signal or the second state signal.Type: ApplicationFiled: January 11, 2024Publication date: July 18, 2024Applicant: STMicroelectronics International N.V.Inventors: Riccardo CONDORELLI, Antonino MONDELLO, Michele Alessandro CARRANO, Michele BOTTARO, Salvatore COSTA, Jacques TALAYSSAT
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Publication number: 20240243712Abstract: A differential pair circuit includes a first branch and a second branch having a common first node. Each of the first and second branches includes at least one transistor having a conduction node directly connected to the common first node. A third branch couples the common first node to a power supply node. The third branch includes a current source in series with a resistive element.Type: ApplicationFiled: January 12, 2024Publication date: July 18, 2024Applicant: STMicroelectronics (Alps) SASInventors: Vratislav MICHAL, Samuel FOULON