Patents Assigned to STMicroelectronics
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Patent number: 12081253Abstract: A method for calibrating the DC operating point of a PWM receiver circuit is disclosed. The PWM receiving circuit includes an envelope detector having a first resistor string, and includes a bias circuit having a second resistor string and a plurality of switches. The second resistor string is coupled between a supply voltage and a reference voltage and functions as a voltage divider. Each switch, when closed, accesses a second voltage at a node of the second resistor string connected to the closed switch. To perform the calibration process, the plurality of switches is closed one at a time, and the second voltage is compared with a first voltage at a first node of the first resistor string. The switch that, when closed, produces the smallest difference between the first voltage and the second voltage remains closed after the calibration process, and is used for demodulating the PWM signal.Type: GrantFiled: July 14, 2023Date of Patent: September 3, 2024Assignee: STMICROELECTRONICS S.R.L.Inventors: Nunzio Spina, Giuseppe Palmisano, Alessandro Castorina
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Patent number: 12079679Abstract: A contactless communication device includes an electronic integrated circuit chip and an antenna coupled to the electronic integrated circuit chip to supply an electric signal for powering the electronic integrated circuit chip. An ambient luminosity detection element is coupled to the electronic integrated circuit chip. An ambient luminosity level measured by the ambient luminosity detection element is supplied to the electronic integrated circuit chip for comparison to a darkness threshold. A contactless communication is authorized only when the measured ambient luminosity level is greater than the darkness threshold.Type: GrantFiled: February 8, 2023Date of Patent: September 3, 2024Assignee: STMicroelectronics (Rousset) SASInventor: Nicolas Cordier
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Patent number: 12081122Abstract: In an embodiment, a switching converter includes: a switching stage configured to receive a direct current input voltage, receive a driving signal for driving the switching stage, and provide a direct current output voltage according to the input voltage and the driving signal; a driving stage configured to provide the driving signal to the switching stage; a current sensing circuit configure to sense an output current provided by the switching stage; and a voltage generation circuit configured to generate at least one supply voltage for powering the driving stage, and adjust the at least one supply voltage according to the output current.Type: GrantFiled: November 22, 2021Date of Patent: September 3, 2024Assignee: STMICROELECTRONICS S.R.L.Inventors: Niccolo′ Brambilla, Sandro Rossi, Valeria Bottarel, Alessandro Nicolosi
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Patent number: 12081888Abstract: The present disclosure relates to a read-out circuit comprising N inputs configured to be connected to N respective outputs of a pixel array of an image sensor, with N being an integer strictly greater than 1; and N analog-to-digital converters organized in K groups, with K being an integer strictly greater than 1 and strictly less than N, and each having a first input coupled to a respective one of the N inputs and a second input. In each group, the second inputs of the analog-to-digital converters of the group are connected together, electrically decoupled from the second inputs of the analog-to-digital converters of the other groups, and configured to receive a first reference signal that is identical for all the analog-to-digital converters of the group.Type: GrantFiled: April 21, 2022Date of Patent: September 3, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventors: Alexandre Mas, Abdessamed Mekki, Cedric Tubert
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Patent number: 12081224Abstract: In an embodiment a method includes generating a low-frequency clock signal having a first frequency, in a standby mode and in a run mode of the CPU, generating a high-frequency clock signal having a second frequency higher than the first frequency, in the run mode, updating a value of the reference time base at each period of the low-frequency clock signal in the standby mode, and accessing the counter register with the high-frequency clock signal in the run mode.Type: GrantFiled: June 17, 2022Date of Patent: September 3, 2024Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grand Ouest) SASInventors: Laurent Meunier, Vincent Pascal Onde
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Patent number: 12080657Abstract: The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP) or a package containing a semiconductor die, with a die embedded within a substrate that is surrounded by an elastomer. The package includes nonconductive layers on surfaces of the substrate and the elastomer as well as conductive layers and conductive vias that extend through these layers to form electrical connections in the package. The package includes surfaces of the conductive material, which may be referred to as contacts. These surfaces of the conductive material are exposed on both sides of the package and allow the package to be mounted within an electronic device and have other electronic components coupled to the package, or allow the package to be included in a stacked configuration of semiconductor dice or packages.Type: GrantFiled: February 13, 2023Date of Patent: September 3, 2024Assignee: STMicroelectronics, Inc.Inventor: Jefferson Sismundo Talledo
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Patent number: 12081128Abstract: A Single Input Dual Output converter includes a first switch coupling an input to a first inductor terminal, a second switch coupling a second inductor terminal to ground, a third switch coupling the second inductor terminal to a positive output, and a fourth switch coupling the first inductor terminal to a negative output. During time-shared control, the negative and positive outputs are independently served by conversion cycles. Each conversion cycle includes: a positive phase with a positive charge phase (closing only the first and second switches), followed by an additional phase (closing only the first and third switches for a given time duration), and followed by a positive discharge phase (closing only the third and fourth switches). Each conversion cycle further includes a negative phase with a negative charge phase (closing only the first and second switches) followed by a negative discharge phase (closing only the second and fourth switches).Type: GrantFiled: August 11, 2022Date of Patent: September 3, 2024Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Gasparini, Mauro Leoncini, Claudio Luise, Alberto Cattani, Massimo Ghioni, Salvatore Levantino
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Patent number: 12081121Abstract: An audio electronic system includes a DC switching converter comprising first and second Zeta converters, each comprising an input stage, an output stage, a first switching stage, and a second switching stage. The input stage of each Zeta converter comprises a respective input inductor having a first terminal electrically coupled to the respective first switching stage. The input inductors of the input stages of the first and second Zeta converters are magnetically coupled in such a way that when current enters the terminal of the input inductor of the first Zeta converter that is coupled to the first switch stage of the first Zeta converter, a voltage induced by the coupled current is positive at the terminal of the input inductor of the second Zeta converter that is coupled to the first switching stage of the second Zeta converter.Type: GrantFiled: May 2, 2023Date of Patent: September 3, 2024Assignee: STMicroelectronics S.r.l.Inventor: Edoardo Botti
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Patent number: 12080631Abstract: The present disclosure is directed to a semiconductor package including a first laser direct structuring (LDS) resin layer and a second LDS resin layer on the first LDS resin layer. Respective surfaces of the first LDS resin layer and the second LDS resin layer are patterned utilizing an LDS process by exposing the respective surfaces to a laser. Patterning the first and second LDS resin layers, respectively, activates additive material present within the first and second LDS resin layers, respectively, converting the additive material from a non-conductive state to a conductive state. The LDS process is followed by a chemical plating step and an electrolytic plating process to form conductive structure coupled to a plurality of die within the first and second LDS resin layers. A molding compound layer is formed on surfaces of the conductive structures and covers the surfaces of the conductive structures.Type: GrantFiled: August 31, 2021Date of Patent: September 3, 2024Assignee: STMICROELECTRONICS S.r.l.Inventor: Luca Grandi
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Publication number: 20240291387Abstract: Provided is a DC-DC converter with galvanic isolation comprising a resonant oscillator coupled to a primary winding of a galvanic isolation transformer. A rectifier is coupled to a secondary winding of the transformer to provide an output voltage. The DC-DC converter comprises a regulation loop configured to regulate an output voltage with respect to a reference voltage by controlling a current flowing in the resonant oscillator as a function of a result of a signal indicative of the comparison between the output voltage and the reference voltage. The resonant oscillator is configured to operate at a frequency, in particular tuned at sub-resonant point, in particular sub-harmonic frequency, below a resonance frequency of the resonant oscillator which maximizes a quality factor of the resonant oscillator, in particular below a resonance frequency of a LC tank circuit comprised in the resonant oscillator which maximizes a quality factor of the LC tank circuit.Type: ApplicationFiled: February 9, 2024Publication date: August 29, 2024Applicant: STMICROELECTRONICS S.r.l.Inventors: Stefano PERROTTA, Salvatore Giuseppe PRIVITERA, Francesco PULVIRENTI
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Publication number: 20240291488Abstract: The present disclosure is directed to a voltage driver, where a combination of first and second resistance blocks controls a differential voltage swing on the outputs of the voltage driver. Variations of an input voltage are compensated by adding different values of the first resistance block to the second resistance block, while keeping a summation of the first and second resistance blocks at a constant value. Three different circuit diagrams are disclosed to generate these different resistances. In each circuit diagram, one or more control signals change the resistance of the combination of first and second resistance blocks. In some embodiments, the value of the second resistance block is changed by the first resistance block to maintain an impedance matching between a transmitter and a receiver, while changing of the first resistance block compensates for the differential voltage swing.Type: ApplicationFiled: February 20, 2024Publication date: August 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Ravinder KUMAR, Saiyid Mohammad Irshad RIZVI
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Publication number: 20240292610Abstract: A memory cell is formed by a PIN diode having three contacts. A breakdown voltage is applied to break down a gate oxide arranged between a region of the PIN diode and a substrate region. The breakdown or non-breakdown state of the gate oxide is determined by applying a read voltage between the anode and the cathode of the diode and determining the value of the corresponding current flowing in the diode.Type: ApplicationFiled: February 24, 2024Publication date: August 29, 2024Applicant: STMicroelectronics International N.V.Inventor: Pascal FORNARA
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Publication number: 20240292612Abstract: A memory cell includes first, second, and third semiconductor regions laterally bounded by insulated conductive walls; a first insulating layer overlaying the first, second, and third semiconductor regions; and a second conductive layer disposed facing a part of each of first, second, and third semiconductor regions. A first top part of the first semiconductor region is first conductivity type doped and faces the second conductive layer. The second semiconductor region includes second top parts forming a transistor with the first insulating layer and second conductive layer. A third top part of the third semiconductor region is second conductivity type doped and faces the second conductive layer. To program the memory cell, an electrical field is applied between the first semiconductor region and the second conductive layer and electrical field is applied between the third semiconductor region and the second conductive layer.Type: ApplicationFiled: February 16, 2024Publication date: August 29, 2024Applicant: STMicroelectronics International N.V.Inventor: Patrick CALENZO
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Publication number: 20240289148Abstract: A method includes executing an application of a scripting language. The application of the scripting language uses first and second packages of an application programming interface (API). The first and second packages extend to each other. The method includes, from a class of the first package, calling and executing first native code of the API to implement a function of a method of the class of the first package. The first native code is in a programming language different from the scripting language. The executing the first native code of the API includes calling a method of a class of the second package. The called method of the class of the second package is executed using a virtual machine of the scripting language. The application of the scripting language may be a Java card application, and the programming language may be a C programming language.Type: ApplicationFiled: February 20, 2024Publication date: August 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Luigi DI MAGGIO, Ettore MIRTO
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Publication number: 20240288680Abstract: A MEMS device includes a semiconductor body with a fixed structure defining a cavity, and a deformable main body suspended on the cavity. A piezoelectric actuator is on the deformable main body, and a piezoelectric sensor element is on the deformable main body, which forms with the deformable main body a strain sensor. The piezoelectric sensor element includes a detection piezoelectric region of aluminum nitride on the deformable main body, and an intermediate detection electrode on the detection piezoelectric region. The deformable main body, the detection piezoelectric region, and the intermediate detection electrode form a first detection capacitor of the strain sensor. The deformable main body, the piezoelectric actuator, and the piezoelectric sensor element form a deformable structure suspended on the cavity and deformable by the piezoelectric actuator, with the strain sensor allowing the deformation of the deformable structure to be detected.Type: ApplicationFiled: February 22, 2024Publication date: August 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Roberto CARMINATI, Tarek AFIFI AFIFI, Carlo Luigi PRELINI, Sonia COSTANTINI
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Publication number: 20240290807Abstract: A body of laser direct structuring (LDS) encapsulating material encapsulates an integrated circuit device and an optical element mounted thereto. Laser activated trace regions and via openings at a first surface of the body are plated to form first conductive lines and first conductive vias. A first passivation layer covers the first conductive lines, the first surface of the body and a portion of the optical element. A second passivation layer covers a thinned backside of the body and integrated circuit device where distal ends of the first conductive vias are exposed. A redistribution layer (RDL) at the second passivation layer includes second conductive lines, pads, and second conductive vias which extend through the second passivation layer to electrically connect the second conductive lines to the distal ends of the first conductive vias. A solder mask layer on the second passivation layer includes openings at the pads of the RDL.Type: ApplicationFiled: January 17, 2024Publication date: August 29, 2024Applicant: STMicroelectronics International N.V.Inventor: Jing-En LUAN
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Publication number: 20240292206Abstract: A notification procedure is executed between an integrated circuit card operating in a communication device and a remote provisioning system. When the notification procedure is interrupted, the integrated circuit card is reset and a reset variable or flag is set. Notification information including a notification message, notification sequence number and a number of said one or more attempts left to perform for the notification procedure is stored in memory. After reset, the notification information is retrieved. If the reset variable or flag is set, the notification sequence number is maintained and a next attempt of the notification procedure is performed. If the reset variable or flag is not set, the notification sequence number is incremented. The reset variable or flag is reset when the notification procedure is completed.Type: ApplicationFiled: February 16, 2024Publication date: August 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Paolo SEPE, Alberto MARZAIOLI
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Publication number: 20240290364Abstract: A device includes memory cells wherein each memory cell has a control input that receives a pulse-width modulated control voltage and an output that delivers a current depending on the control voltage and on a weight programmed in the memory cell. A node receives, during a first time period, the currents of the memory cells. A first circuit delivers an output determined by a total quantity of current received by the node during the first time period. For each memory cell, a second circuit receives a digital word and delivers, during the first time period, the pulse-width modulated control voltage at a first level only during a second time period determined by the digital word.Type: ApplicationFiled: February 14, 2024Publication date: August 29, 2024Applicant: STMicroelectronics International N.V.Inventors: Leonardo VALENCIA RISSETTO, Alin RAZAFINDRAIBE, Xavier LECOQ, Christophe FOREL
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Publication number: 20240289116Abstract: The present disclosure relates to a method for updating multiple executable load files in a secure element comprising: receiving at least one command for performing an update session of multiple executable load files, each executable load file associated with an application identifier; before starting an update of an executable load file: checking whether this executable load file is associated with an application identifier identical to the one of an executable load file for which an update is already ongoing, and proceeding with the update of the executable load file if its application identifier is new in view of the application identifier of each executable load file for which an update is already ongoing, or rejecting the update of this executable load file if it is associated with an application identifier identical to the one of an executable load file that has already been updated in this update session.Type: ApplicationFiled: February 9, 2024Publication date: August 29, 2024Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Paolo SEPE, Luigi TERRONE, Alfonso TRAMONTANO
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Patent number: 12073308Abstract: Embodiments are directed towards a hardware accelerator engine that supports efficient mapping of convolutional stages of deep neural network algorithms. The hardware accelerator engine includes a plurality of convolution accelerators, and each one of the plurality of convolution accelerators includes a kernel buffer, a feature line buffer, and a plurality of multiply-accumulate (MAC) units. The MAC units are arranged to multiply and accumulate data received from both the kernel buffer and the feature line buffer. The hardware accelerator engine also includes at least one input bus coupled to an output bus port of a stream switch, at least one output bus coupled to an input bus port of the stream switch, or at least one input bus and at least one output bus hard wired to respective output bus and input bus ports of the stream switch.Type: GrantFiled: February 2, 2017Date of Patent: August 27, 2024Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.r.lInventors: Thomas Boesch, Giuseppe Desoli