Patents Assigned to STMicroelectronics
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Publication number: 20130138975Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.Type: ApplicationFiled: January 28, 2013Publication date: May 30, 2013Applicant: STMicroelectronics S.A.Inventor: STMicroelectronics S.A.
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Publication number: 20130136352Abstract: A method of processing digital images by transforming a set of pixels from a three-dimensional space to a normalized two-dimensional space, determining a membership class and membership class level of each pixel in the set of pixels, and selectively modifying colors of pixels in the set of pixels based on the determined membership classes and membership class levels.Type: ApplicationFiled: January 14, 2013Publication date: May 30, 2013Applicant: STMicroelectronics S.r.l.Inventor: STMicroelectronics S.r.l.
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Patent number: 8453098Abstract: A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.Type: GrantFiled: March 30, 2009Date of Patent: May 28, 2013Assignee: STMicroelectronics, Inc.Inventor: Razak Hossain
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Patent number: 8451035Abstract: The present disclosure provides an emulator mapping process on a system-on-a-chip (SoC) for debugging. The implementation reduces manual intervention and makes the emulation mapping process very generic and technology independent and hence it reduces overall project cycle time. In the present disclosure, the SoCs containing analog delay locked loops are made suitable for emulation by configuring analog delay locked loop module in parallel with a synthesizable delay logic module. Further, selection logic is provided to select any one of the module at a time.Type: GrantFiled: December 15, 2010Date of Patent: May 28, 2013Assignee: STMicroelectronics International NVInventors: Prateek Sikka, Rajesh Chopra, Manoj Yadav
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Patent number: 8452992Abstract: An embodiment of a method and system are provided for managing both system resources and power consumption of a computer system, involving different layers of the system: an application layer, a middle layer where the operating system is running and where a power manager is provided, and a hardware layer used for communicating with the hardware devices. Hardware devices have different operating modes which provide distinct trade-offs between performances and power consumption. Performance requirements defined at the level of the application layer, as well as the device power status of the system, set constraints on the system resources. The middle layer power manager may be in charge of retrieving performance requirements in form of constraints set on system parameters, aggregating these constraints opportunely and communicating corresponding information to the device drivers which may then select a best operating mode.Type: GrantFiled: June 29, 2010Date of Patent: May 28, 2013Assignee: STMicroelectronics S.r.l.Inventors: Stefano Bosisio, Patrick Bellasi, Matteo Carnevali, David Siorpaes, William Fornaciari
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Patent number: 8451629Abstract: A circuit for an oscillator structured to drive a control device of a switching resonant converter; the converter having a switching circuit structured to drive a resonant load provided with at least one transformer with at least a primary winding and at least a secondary winding. The control device structured to drive the switching circuit, and the converter structured to convert an input signal into an output signal, the integrated circuit includes a first circuit structured to charge and discharge a capacitor by a first current signal such that the voltage at the ends of the capacitor is between first and second reference voltages, the current signal having a second current signal indicating the output voltage of the converter; the integrated circuit including a second circuit structured to rectify a signal indicating the current circulating in the primary winding.Type: GrantFiled: December 27, 2010Date of Patent: May 28, 2013Assignee: STMicroelectronics S.r.l.Inventor: Claudio Adragna
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Patent number: 8448332Abstract: Electronic modules are transported with respect to equipment for manipulating and testing electronic modules. The transport is formed from a thin support having openings for receiving electronic modules. A locating mechanism associated with the thin support serves to locate the support relative to transport and testing equipment. A mechanism is further provided for holding the received electronic modules within the openings during transport and testing.Type: GrantFiled: January 28, 2009Date of Patent: May 28, 2013Assignee: STMicroelectronics (Grenoble 2) SASInventors: Philippe Planelle, Rene Monnet
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Patent number: 8448494Abstract: An electronic microbalance made in a semiconductor body accommodating an oscillating circuit adjacent to a diaphragm. A stack formed by a first electrode, a second electrode, and a piezoelectric region arranged between the first and the second electrode extends above the diaphragm. Any substance that deposits on the stack causes a change in the mass of the microbalance and thus in the resonance frequency of a resonator formed by the microbalance and by the oscillating circuit and can thus be detected electronically. A chemical sensor is obtained by forming a sensitive layer of a material suitable for binding to target chemicals on the stack. The sensitivity of the microbalance can be increased by making the first electrode of molybdenum so as to increase the piezoelectric characteristics of the piezoelectric region.Type: GrantFiled: December 29, 2009Date of Patent: May 28, 2013Assignee: STMicroelectronics S.R.L.Inventors: Ubaldo Mastromatteo, Flavio Francesco Villa, Gabriele Barlocchi
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Patent number: 8451016Abstract: A testing mechanism for testing magnetically operated microelectromechanical system (MEMS) switches at a wafer level stage of manufacture includes an electromagnetic fixture configured to be received in a standard probe ring. The electromagnetic fixture is rotatable, relative to the probe ring, to permit adjustment of orientation of a generated magnetic field relative to the MEMS devices of a subject wafer. The testing mechanism also includes a probe card with probes positioned to contact test pads on the subject wafer. During operation, the probe card is positioned over the wafer to be tested, with the test probes in electrical contact with respective contact pads of the wafer, and the electromagnetic fixture is positioned above the probe card. An electrical potential is applied across the switches on the subject wafer, and the electromagnetic fixture is energized at selected levels of power and duration.Type: GrantFiled: December 30, 2009Date of Patent: May 28, 2013Assignee: STMicroelectronics Pte Ltd.Inventors: Ravi Shankar, Olivier Le Neel
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Patent number: 8451726Abstract: An embodiment of a system for physical link adaptation in a wireless communication network such as e.g., a WLAN, selectively varies the physical mode of operation of the transmission channels serving the mobile stations in the network. The system includes an estimation module to evaluate transmission losses due to collisions as well as transmission losses due to channel errors over the transmission channel, and an adaptation module to select the physical mode of operation of the transmission channel as a function of the transmission losses due to collisions and to channel errors as evaluated by the estimation module.Type: GrantFiled: December 31, 2008Date of Patent: May 28, 2013Assignee: STMicroelectronics S.r.l.Inventors: Nicola Baldo, Simone Merlin, Andrea Zanella, Michele Zorzi, Davide Siorpaes, Ida Polato, Renato Maguolo, Sandro Maguolo
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Patent number: 8451283Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. The coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.Type: GrantFiled: April 6, 2012Date of Patent: May 28, 2013Assignee: STMicroelectronics SAInventors: Patrice Couvert, Anthony Philippe
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Patent number: 8452088Abstract: A method of classification for a content-based digital-image, including: defining a set of low-level features describing the semantic content of the image, the features being quantities obtainable from the image by means of logico-mathematical expressions that are known beforehand, and the choice of said features depending upon the image classes used for the classification; indexing an image to be classified, with the purpose of extracting therefrom a feature vector, the components of which consist of the values assumed, in the image, by said low-level features; splitting the feature space defined by the low-level features into a plurality of classification regions, to each one of the regions there being associated a respective image class, and each classification region being the locus of the points of the feature space defined by a finite set of conditions laid on at least one component of the feature vector; associating the feature vector to the feature space; identifying, among the classification regions,Type: GrantFiled: November 15, 2000Date of Patent: May 28, 2013Assignee: STMicroelectronics S.r.l.Inventors: Mauro De Ponti, Raimondo Schettini, Carla Brambilla, Anna Valsasna, Gianluca Ciocca
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Patent number: 8453238Abstract: A method for protecting a key used, by an electronic circuit, in a symmetrical algorithm for ciphering or deciphering a message, including the steps of complementing to one the key and the message; executing the algorithm twice, respectively with the key and the message and with the key and the message complemented to one, the selection between that of the executions which processes the key and the message and that which processes the key and the message complemented to one being random; and checking the consistency between the two executions.Type: GrantFiled: November 2, 2010Date of Patent: May 28, 2013Assignee: STMicroelectronics (Rousset) SASInventors: Pierre-Yvan Liardet, Fabrice Marinet
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Patent number: 8451946Abstract: A method is for decoding a pulse signal modulated through a transmitted reference modulation scheme. The modulated pulse signal may include, repetitively, a reference pulse followed by an information pulse delayed with a delay. The method may include subtracting or adding from the modulated pulse signal, a version of the modulated pulse signal delayed with the delay for obtaining a processed signal, and performing a non-coherent detection on the processed signal.Type: GrantFiled: December 14, 2005Date of Patent: May 28, 2013Assignee: STMicroelectronics N.V.Inventors: Gian Mario Maggio, Chiara Cattaneo, Philippe Rouzet
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Publication number: 20130127454Abstract: A magnetic field sensor, including a Hall magnetic sensor, formed within a first die and configured to detect a first magnetic field, and a first anisotropic magnetoresistive magnetic sensor, having a first anisotropic magnetoresistive transducer, formed within a second die and configured to generate an electrical measurement quantity as a function of a second magnetic field. An electronic reading circuit formed within the first die, is electrically connected to the first anisotropic magnetoresistive transducer, and provides a first measure indicating the second magnetic field, on the basis of the electrical measurement quantity. The first and second dice are fixed with respect to one another and have main surfaces parallel to the same reference plane. The first magnetic field being oriented in a first direction perpendicular to the reference plane and the second magnetic field being oriented in a second direction parallel to the reference plane.Type: ApplicationFiled: November 21, 2012Publication date: May 23, 2013Applicant: STMicroelectronics S.e.I.Inventor: STMicroelectronics S.r.I.
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Publication number: 20130130492Abstract: Solder joint reliability in an integrated circuit package is improved. Each terminal of a quad, flat, non-leaded integrated circuit package is formed having portions that define a solder slot in the bottom surface of the terminal. An external surface of the die pad of the integrated circuit package is also formed having portions that define a plurality of solder slots on the periphery of the die pad. When solder is applied to the die pad and to the terminals, the solder that fills the solder slots increases the solder joint reliability of the integrated circuit package.Type: ApplicationFiled: November 8, 2012Publication date: May 23, 2013Applicant: STMicroelectronics, Inc.Inventor: STMicroelectronics, Inc.
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Publication number: 20130128111Abstract: An image processing system includes an image reconstruction unit. The image reconstruction unit is configured to receive an image at a first resolution, apply the image to a look-up table and output a version of the image at a second resolution. The second resolution includes a higher resolution than the first resolution. In addition, the look-up table is generated inputting a plurality of training images; classifying, into a number of classes, a plurality of images patches corresponding to each of the plurality of training images; re-classifying the number of classes into a final class; and synthesizing filters corresponding to each of the class into a final filter value.Type: ApplicationFiled: December 29, 2011Publication date: May 23, 2013Applicant: STMicroelectronics (CANADA), Inc.Inventor: Eduardo R. Corral-Soto
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Publication number: 20130127549Abstract: An electronic circuit including two ring oscillators, wherein the output of each ring oscillator is looped back on the input of this same oscillator as well on the input of the other oscillator. The application of such a circuit to the detection of a dynamic disturbance.Type: ApplicationFiled: November 6, 2012Publication date: May 23, 2013Applicant: STMicroelectronics (Rousset) SASInventor: STMicroelectronics (Rousset) SAS
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Publication number: 20130128122Abstract: A method and apparatus are disclosed for identifying and removing banding artifacts (i.e., false contours) resulting from insufficient bit depth caused by digital image quantization, conversion, and/or compression. This method includes: explicitly identifying texture block and flat block; de-termination of filter window sizes with the consideration of handling transitions between texture block and flat block; de-banding filtering with edge protection; and noise shaping according to de-banding filter result.Type: ApplicationFiled: November 23, 2011Publication date: May 23, 2013Applicant: STMicroelectronics Asia Pacific Pte Ltd.Inventors: Haiyun WANG, Lucas HUI
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Publication number: 20130128656Abstract: A static random access memory (SRAM) device includes a memory array of a plurality of memory cells, a controller that receives an external clock signal formed by a succession of external pulses and generates an internal clock signal formed by a succession of internal pulses, and a driving circuit that receives the internal clock signal. The controller is operable in a first mode, wherein the controller generates, for each external pulse, a corresponding internal pulse and the controller controls the driving circuit so that the driving circuitry carries out one access to the memory array for each internal pulse. The controller is further operable in a second mode, wherein the controller generates, for each external pulse, a pair of internal pulses, and the controller controls the driving circuitry so that, for each pair of internal pulses, the driving circuitry writes a first data item in a set of memory cells, and then reads the set of memory cells, so as to acquire a second data item.Type: ApplicationFiled: November 20, 2012Publication date: May 23, 2013Applicants: STMicroelectronics S.r.l., STMicroelectronics PVT LTD.Inventors: STMicroelectronics PVT LTD., STMicroelectronics S.r.l.