Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is coupled as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

Abstract: An apparatus and method are disclosed for temperature measurement that includes performing a first ?Vbe measurement of a first temperature of a diode circuit comprising a transistor and, subsequently, performing a first Vbe measurement of a second temperature of the diode circuit. A temperature difference is calculated between the second temperature and the first temperature. If the temperature difference is not greater than a predetermined amount, a second Vbe measurement of a third temperature of the diode circuit is subsequently performed. If the temperature difference is greater than the predetermined amount, a second ?Vbe measurement of the second temperature of the diode circuit is performed.

Abstract: An integrated circuit including an insulating layer having first and second opposite surfaces. The circuit includes, in a first area, first conductive portions of a first conductive material, located in the insulating layer, flush with the first surface and continued by first vias of the first conductive material, of smaller cross-section and connecting the first conductive portions to the second surface. The circuit further includes, in a second area, second conductive portions of a second material different from the first conductive material and arranged on the first surface and second vias of the first conductive material, in contact with the second conductive portions and extending from the first surface to the second surface.

Abstract: Methods and systems are described for enabling display system data transmission during use. An integrated circuit package includes input interface circuitry configured to receive an audio-video data stream having a video signal and timing information and timing extraction circuitry that can identify blanking patterns for the video signal. The package includes input processing circuitry for receiving audio-video signal and converting the audio-video data stream input into a low voltage differential signal (LVDS). The package includes a timing controller having timing extraction circuitry, a set of symbol buffers, a scheduler, and timing control circuitry. All configured to implement LVDS data transfer and in some implementation enable point to point data transfer from data buffers to associated column drivers.

Abstract: A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.

Abstract: A voltage signal multiplexer includes a control and bias stage to generate at least one control and bias signal as a function of first and second selection signals and first and second input voltage signals. The multiplexer further comprises a switching stage configured to receive the at least one first control and bias signal and to generate therefrom, on an output terminal, an output signal having the first input voltage signal in response to the first and the second selection signals indicating the selection of the first input voltage signal, and having the second input voltage signal in response to the first and the second selection signals indicating the selection of the second input voltage signal. The switching stage is also configured to place the output terminal in a high-impedance condition in response to the first and the second selection signals indicating the high-impedance condition.

Abstract: A leadless semiconductor package includes a package body on a leadframe that includes a die paddle and a plurality of high-aspect-ratio leads, each coupled at a first end to a contact pad of the package, and at a second end to a semiconductor die mounted to the die paddle. During manufacture of the package, molding compound is deposited over a face of the leadframe on which the die paddle and leads are positioned. After the molding compound is cured, a back side of the leadframe is etched to isolate the die paddle and leads, and to thin a portion of each of the leads. Back surfaces of the leads remain exposed at a back face of the body. The thinned portions of the leads are covered with a dielectric. During manufacture of the leadframe, a parent substrate is etched to define the die paddle and a plurality of leads on one side of the substrate and a plurality of cavities on the opposite face.

Abstract: A memory management device including a plurality of outputs, each output configured to interface to respective one of a plurality of memories; and a controller configured to cause each buffer allocated to the memories to be divided up substantially equally between each of the plurality of memories.

Abstract: The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of the supply voltage or by the intermediary of a reception or emission terminal of a data or clock signal. Applicable in particular to electronic tags comprising a reduced number of interconnection terminals.

Abstract: A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.

Abstract: A request routing circuit includes m inputs for receiving m input request signals and n outputs for outputting a set of n output request signals. A routing subsystem within the request routing circuit is provided between the m inputs and the n outputs and comprises k inputs and n outputs, where m is greater than k, and where the routing subsystem is configured to operate over a plurality (m/k, rounded up to the next integer) of cycles to provide the set of n output request signals based on the m inputs to the n outputs.

Abstract: A semiconductor device with vertical current flow includes a body having a substrate made of semiconductor material. At least one electrical contact on a first face of the body. A metallization structure is formed on a second face of the body, opposite to the first face. The metallization structure is provided with metal vias, which project from the second face within the substrate so as to form a high-conductivity path in parallel with portions of said substrate.

Abstract: A system and method for optimal allocation of bandwidth in a multichannel transmission channel. In an embodiment, a system may allocate a specific amount of bandwidth in the transmission channel in order to maximize the value of the data that is transmitted on a per-channel basis. Typically, a transmission channel has enough bandwidth to accommodate the minimum bandwidth for all data across all channels. The excess bandwidth may be allocated in an optimal manner so as to provide additional bandwidth for the most valuable channels. The maximum allocation of bandwidth is a point in which allocating additional bandwidth to a channel does not yield any additional value. Such an allocation may be accomplished using an iterative analysis of the available bandwidth and a microeconomic-based analysis of the subjective value of each channel.

Abstract: According to an embodiment, a receiver, system and method for channel estimation in a communications system utilizing multiple transmit antennas are provided. The receiver comprises an antenna node operable to receive a signal that includes a superposition of at least a first signal corresponding to a first sequence and a second signal corresponding to a second sequence; and a channel estimator, coupled to the antenna node, operable to correlate the received signal with at least one of the first and second sequences, to determine at least one boundary between at least two waveforms resulting from the correlation, and to calculate using the boundary and the at least two waveforms a first channel response corresponding to the first signal and a second channel response corresponding the second signal. Channel estimates are determined based on determined boundaries and may be smoothed by a Savitzky-Golay filter in the frequency domain. The variance of additive white Gaussian noise (AWGN) may also be estimated.

Abstract: The disclosure concerns a method of simulating the image projected by a mask during photolithography including determining by a processor (702), taking into account the thickness of a masking layer of a mask, a near-field transmission amplitude curve of light passing through the mask across at least one pattern boundary in the initial mask layout; calculating by the processor, for each of a plurality of zones, average values of the curve; and simulating by a simulator (708) the image projected by the initial mask layout during the photolithography based on the average values.

Abstract: A wafer level packaged integrated circuit includes an array of contacts, a silicon layer and a glass layer. The silicon and glass layers are bonded together to form a bonding material layer therebetween. The bonding material layer includes gaps between the silicon layer and the glass layer at areas where no bonding material is present. An array of contacts is adjacent the semiconductor layer on a side thereof opposite the bonding layer. The wafer level packaged integrated circuit is provided with additional bonding material layer portions within the gaps and aligned with at least some of the contacts. When the wafer level packaged integrated circuit is configured as an image sensor or display having a pixel array, the additional bonding material layer portions are not used in an area of the pixel array.

Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.

Abstract: An embodiment of a power device having a first current-conduction terminal, a second current-conduction terminal, a control terminal receiving, in use, a control voltage of the power device, and a thyristor device and a first insulated-gate switch device coupled in series between the first and the second conduction terminals; the first insulated-gate switch device has a gate terminal coupled to the control terminal, and the thyristor device has a base terminal. The power device is further provided with: a second insulated-gate switch device, coupled between the first current-conduction terminal and the base terminal of the thyristor device, and having a respective gate terminal coupled to the control terminal; and a Zener diode, coupled between the base terminal of the thyristor device and the second current-conduction terminal so as to enable extraction of current from the base terminal in a given operating condition.

Abstract: A switched charge storage element integrator in a continuous or discrete time circuit, the integrator including a differential input amplifier, a first 2-terminal charge storage element, a second 2-terminal charge storage element, and a plurality of controlled switches. The differential input amplifier is coupled to a capacitor and a resistor and configured as an inverting integrator. An inverting terminal of the amplifier is coupled to two controlled switches. A non-inverting terminal of the amplifier is coupled to a reference voltage. The first and second switched charge storage element blocks are alternatingly coupled to the inverting terminal INM of the amplifier XOPA during the active state of a second clock signal and a first clock signal, respectively, for making the supply noise continuous and eliminating its dependency on the clock phases, thereby zeroing its convolution with the clock signal.

Abstract: A rectifier building block has four electrodes: source, drain, gate and probe. The main current flows between the source and drain electrodes. The gate voltage controls the conductivity of a narrow channel under a MOS gate and can switch the RBB between OFF and ON states. Used in pairs, the RBB can be configured as a three terminal half-bridge rectifier which exhibits better than ideal diode performance, similar to synchronous rectifiers but without the need for control circuits. N-type and P-type pairs can be configured as a full bridge rectifier. Other combinations are possible to create a variety of devices.