Abstract: The invention concerns a circuit comprising: a first circuit block (302) adapted to receive a first clock signal (CLK1) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block (304) adapted to receive a second clock signal (CLK2) and to provide a second output data signal at a time determined by said second clock signal; a clock bus (314) coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit (312) coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.

Abstract: The trimming circuit includes a plurality of trimmable resistances that may be coupled among them, each resistance being connected in parallel to a respective fuse. The trimming circuit allows burning any number of fuses according to a fixed trimming sequence using only one or two dedicated pins because it includes an input diode-connected transistor and a plurality of trimming transistors of different sectional area, each connected to force current throughout a respective one of the shunt fuses and coupled to the input diode-connected transistor such to mirror the current flowing therethrough. The fuses of the trimming circuit may be burnt by applying a trimming voltage to the diode-connected input transistor with a voltage generator connected between a dedicated pin of the circuit and a terminal at a reference potential, such to force a current therethrough as long as the mirrored currents flowing throughout the fuses burn them.

Abstract: An embodiment of a method is disclosed for encoding a digital video signal including a first video sequence and a second video sequence jointly forming a stereo-view digital video signal. The method includes: subjecting the first video sequence to discrete cosine transform, quantization and run-length coding to produce a sequence of blocks of non-zero digital levels representative of the first video sequence, subjecting the second video sequence to discrete cosine transform, quantization, run-length coding and variable length coding to produce digital messages representative of the second video sequence, merging the bits of the digital messages into the sequence of blocks of digital levels by substituting the bits of the digital messages for respective Least Significant Bits of e.g. the last digital level in the blocks representative of the first video sequence to produce an encoded digital video signal representative of the first video sequence and the second video sequence.

Abstract: A circuit comprises a frequency divider coupled to receive an oscillating signal generated by an oscillator and a division ratio and configured to divide the oscillating signal by the division ratio into a clock signal; a temperature compensation circuit configured to measure a temperature of the oscillator and generate a division ratio to be provided to the frequency divider and a first value on the basis of the measured temperature; and a control system configured to control connection between a calibration element and the oscillator based on the first value and the oscillating signal of the oscillator.

Abstract: The semiconductor device for protection from electrostatic discharges comprises several modules (MDi) for protection from electrostatic discharges comprising triggerable elements (TRi) coupled with triggering means, the said modules being connected between two terminals by the intermediary of a resistive network (R). A common semiconductor layer contacts all of the modules, each triggerable element (TRi) having at least one gate (GHi), and the triggering means comprise a single triggering circuit (TC) common to all of the triggerable elements and whose output is connected to the gates of all of the triggerable elements.

Abstract: Disclosed is a low drop-out voltage regulator circuit with a distributed output network coupled to a pixel array for use in image sensor circuitry. The regulator circuit comprises voltage regulating circuitry and a distributed output network, wherein the distributed output network comprises drive transistors disposed along and connected between a supply track and an output track. The spatial distribution of the drive transistors improves heat dissipation within the regulator circuit, and a combination of low current flow and regulated output voltage reduces IR drop across the output track. The improved heat dissipation increases device lifespan and performance, whereas the reduction in IR drop across the output track provides better pixel response, readout uniformity, and image quality.

Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.

Abstract: An electrically programmable and erasable non-volatile memory point may have at least one floating-gate transistor connected to a bit line and to a ground line, and may be programmed with a programming voltage. In an erase phase of the memory point, a first, negative, voltage may be applied to the bit line and to the ground line. The absolute value of the first voltage may be smaller than a threshold value of a PN diode. A second positive voltage which is smaller than the programming voltage may be applied to the control gate of the floating-gate transistor. The difference between the second voltage and the first voltage may be equal to the programming voltage, and, in a writing phase, the first negative voltage may be applied to the control gate of the floating-gate transistor, and the second voltage may be applied to the bit line.

Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generates PWM control signals for controlling operation of the first and second transistors. The control signals are generated responsive to source PWM signals processed through programmable delay timers to generate set/reset control signals which set an output PWM control signal duty cycle.

Abstract: The present disclosure relates to a method of processing an interrupt comprising a peripheral unit sending an interrupt, the interrupt being intended for a virtual unit executed by a processing unit, transmitting the interrupt to an interrupt control unit coupled to a processing unit, and the interrupt control unit storing the interrupt in an interrupt register. According to an embodiment of the present disclosure, the interrupt is transmitted to the interrupt control unit in association with an identifier of the virtual unit receiving the interrupt, the interrupt register in which the interrupt belonging to a set of registers is stored comprising one interrupt register per virtual unit likely to be executed by the processing unit, the interrupt being transmitted to the processing unit if the virtual unit receiving the interrupt is being executed by the processing unit.

Abstract: In BLDC motors driven via sensorless techniques, the BEMF signals in the motor coils may be used to detect the position of the motor such that speed of the motor may be accurately controlled. When detecting the BEMF signals, however, small perturbations occur which negatively impact the rotational torque of the motor. As a result, torque ripple may occur at regular intervals which may result in inefficiencies as well as audible noise. In various embodiments as described herein, the sampling of the BEMF signals may be done so at pseudo-random intervals such that the overall spectral energy that presents from the BEMF detections may be reduced at specific frequencies (such as fundamental sampling frequencies and harmonics thereof) and spread out over many more frequencies. Thus, despite the overall spectral energy being the same, the amplitude of any given frequency is lower as the sampling of the BEMF is less periodic.

Abstract: A method of generating a reset signal for an integrated circuit without a dedicated reset pin includes calibrating a first clock pulse from a clock signal, measuring a second clock pulse from the clock signal, measuring a third clock pulse from the clock signal, and generating an internal reset signal if the first clock pulse width is longer than a predetermined minimum clock pulse width, if the second clock pulse is within an expected first value range, and if the third clock pulse is within an expected second value range.

Abstract: A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes for which the access to the areas is authorized or forbidden is associated with each of these areas.

Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake at a temperature lower or equal to 800° C., a subsequent deposition step will prevent deposition in the first surface region. This allows selective deposition in the second surface region, which is not doped with the Boron (or doped with another dopant or not doped). Several devices are, thus, provided. The method saves a usual photolithography sequence, which according to prior art is required for selective deposition of Si or SiGe in the second surface region.

Abstract: A communication system transmits data from a first circuit over a communication channel to a second circuit, the data having a first priority and a second priority. The communication system includes a separation circuit, a first-in first-out (FIFO) memory, and a control circuit.

Abstract: An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors.

Abstract: A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes authorized or forbidden as a content of the areas is associated with each of these areas.

Abstract: An embodiment of an integrated scanner apparatus, includes a support surface for objects to be scanned, a scanner unit to perform a scanning movement relative to the support surface to capture images of portions of objects to be scanned, and a printer unit carried by a carriage mobile with respect to said support surface, wherein said scanner unit is carried by said carriage carrying said printer unit to be imparted said scanning movement by said carriage.

Abstract: A semiconductor packaging process includes drilling apertures in a reconstituted wafer, then filling the apertures with conductive paste by wiping a quantity of the paste across a back surface of the wafer so that paste is forced into the apertures. The paste is cured to form conductive posts. The wafer is thinned, and redistribution layers are formed on front and back surfaces of the wafer, with the posts acting as interconnections between the redistribution layers. In an alternative process, blind apertures are drilled. A dry film resist is applied to the front surface of the wafer, and patterned to expose the apertures. Conductive paste is applied from the front. To prevent paste from trapping air pockets in the apertures, the wiping process is performed under vacuum. After curing the paste, the wafer is thinned to expose the cured paste in the apertures, and redistribution layers are formed.

Abstract: A method of performing a cryptographic operation including: receiving a plurality of binary input values; splitting the binary input values into a plurality of non-binary digits of base r, where r is an integer greater than 2 and not equal to a power of 2; and performing, by a cryptographic block on each of the plurality of non-binary digits, a different modulo r operation to generate at least one output digit) of base r.