Abstract: An energy scavenging interface has an input port receiving an electrical signal from a storage element of a transducer, and an output port supplying an output signal to an electrical load. The interface includes a first switch receiving the input signal; a second switch that supplying the output signal; and control logic configured to close the first switch and open the second switch for a first time interval having at least a first temporal duration and until current through the first switch reaches a threshold. A scaled copy of a peak value of current through the first switch is obtained during the first time interval. The control logic is further operable to open the first switch and close the second switch to supply current to the electrical load as long as the current of the output signal remains greater than the value of said scaled copy of the peak value.

Abstract: Embodiments of the present invention relate to a system for clock synthesis or data timing recovery. No analog continuous time oscillator is required, all the building blocks of a Frequency Locked Loop/Phase Locked Loop belonging in the digital discrete time domain. From a system-level perspective, the system is characterized by its strong non-linear behavior due to the intrinsic nature of some building blocks. This inherent non-linearity is responsible for some unusual, attractive property of the complete system. The system is able to multiply the input frequency clock by an arbitrarily large factor, ensuring in any case the convergence of the algorithm in two reference clock cycles.

Abstract: A micro scale includes one substrate forming a first zone constituting a first terminal, one conducting vibrating beam which has two opposite ends affixed on two supporting areas on the substrate, the conductive beam forming a second terminal; wherein the conductive beam is made of polymer gel having metallic microparticles in low quantity so as to avoid any contamination of a biological material to measure, the density of the metallic microparticles being high enough to achieve electrical conduction of the second terminal. A manufacturing process of such a micro scale circuit is also provided.

Abstract: A coexistence communications method for use between wireless networks includes adopting a super-frame structure for use in a wireless network having a plurality of frames, wherein a first frame includes a super-frame preamble, a super-frame control header, a data portion, and a regular self-coexistence window, an intermediate frame includes an OFDM symbol, a data portion, and a regular self-coexistence window, and a last frame includes an OFDM symbol, a data portion, and a joining self-coexistence window, using the self-coexistence windows to exchange inter-wireless network co-existence messages, and using a last reserved self-coexistence window to announce intra-wireless network negotiation decisions.

Abstract: A surface of a support comprising through micropassages is brought into contact with an aqueous solution comprising a plurality of particles in suspension and a pad. A pressure perpendicular to the plane of the support, between the pad and the surface of the support, and a relative movement of the pad and of the surface in a direction parallel to the plane of the support are applied. At least one particle is thus introduced in each microgap to form a porous material therein.

Abstract: A method manufactures an electronic device comprising a MEMS device overmolded in a protective casing. The MEMS device includes an active surface wherein a portion of the MEMS device is integrated, and is sensitive, through a membrane, to chemical/physical variations of a fluid. Prior to the molding step, at least one resin layer is formed on at least one region overlying the active surface in correspondence with the membrane. After, at least one portion of at least one resin layer is removed from at least one region, so that in the region an opening is formed, through which the MEMS device is activated from the outside of the protective casing.

Abstract: A startup circuitry connected to a main circuit which has at least an output terminal connected to its feedback terminal by a feedback loop. The startup circuitry is connected to the main circuit in such a manner to break the feedback loop, by having a first circuit node connected to said output terminal of said main circuit and a second circuit node connected to its feedback terminal, said startup circuitry providing a correct output voltage value during the startup phase of said main circuit.

Abstract: A process for manufacturing a MOS device includes forming a semiconductor layer having a first type of conductivity; forming an insulated gate structure having an electrode region, above the semiconductor layer; forming body regions having a second type of conductivity, within the semiconductor layer, laterally and partially underneath the insulated gate structure; forming source regions having the first type of conductivity, within the body regions; and forming a first enrichment region, in a surface portion of the semiconductor layer underneath the insulated gate structure. The first enrichment region has the first type of conductivity and is set at a distance from the body regions. In order to form the first enrichment region, a first enrichment window is defined within the insulated gate structure, and first dopant species of the first type of conductivity are introduced through the first enrichment window and in a way self-aligned thereto.

Abstract: A processing system, such as typically a CPU, is used for converting a digital signal organized in pixels, such as a video signal, between a first format and a second multiple-description format. The system comprises at least one input register and at least one output register, and is configured via instructions, that can be constituted at least in part by instructions of a SIMD type, so as to: order the pixels of the signal to be converted in a set of input registers; and take selectively the pixels from the aforesaid set of input registers and place them in an orderly way in at least one output register.

Abstract: A data interleaving device is provided that includes an input, an output, and a data interleaver coupled to the input and the output. The input receives data originating from a plurality of processing blocks. The output transfers interleaved data to the plurality of processing blocks. The data interleaver includes a controller, at least one interconnection module, and a plurality of memories. The controller prepares a data-to-memory assignment data structure. The at least one interconnection module switches data in parallel according to the data-to-memory assignment data structure and acts identically on all data switched simultaneously in parallel. The plurality of memories store the switched data. The data interleaver interleaves data received from the input and provides the interleaved data at the output.

Abstract: A method for communications between neighboring wireless cells such as wireless regional area networks operating according to IEEE 802.22 specifications. The method involves scheduling inter-base station communications for over-the-air connections to allow neighboring base stations to communicate in environments where a single available channel is shared between the neighboring cells or where two or more channels used by two or more neighboring cells. In some embodiments, a bridge system, such as a bridge consumer premise equipment (CPE), positioned in an area of coverage overlap between two cells is used for inter-base station communications, and allocation and scheduling of bandwidth on the utilized channels is performed to provide interference free communications between the base stations. Existence announcements are provided in coexistence time slots and requests for bandwidth such as reserved and additional time slots are transmitted between the base stations using the coexistence time slots.

Abstract: Method for transmitting information in a multi-band OFDM system, comprising delivering according to a given communication standard an initial data stream (IDS), splitting (11) said initial data stream into a chosen number of elementary data streams and simultaneously transmitting (12) said elementary data streams according to said communication standard on said communication medium (MD) within different respective sub-bands (SBi). These sub-bands all blong to the same band group. Proposal based on the MBOA standard.

Abstract: In a method for producing a control signal for regulating a drive current for driving an LED, a current through the LED is sensed, wherein the LED is driven by a power converter output, and wherein an output voltage of the power converter is proportionately controlled by a control signal. Next, a power supply voltage is sensed. The control signal is produced for the power converter, wherein the control signal is proportional to a difference between a reference voltage and the current through the LED. The control signal is then offset in response to the power supply voltage to reduce the current through the LED as the power supply voltage drops.

Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

Abstract: A method of estimating a global motion vector representative of the motion of a first digital image with respect to a second digital image, the first and the second image forming part of a sequence of images and being made up of, respectively, a first and a second pixel matrix. The method estimates the global motion vector on the basis of the estimate of at least one motion vector of at least one region of the first image representative of the motion of the at least one region from the first image to the second image and comprising phases of: subdividing the at least one region of the first image into a plurality of pixel blocks, assigning to each block of the plurality a respective weighting coefficient calculated on the basis of a respective inhomogeneity measure, and estimating the at least one motion vector of said at least one region on the basis of the weighting coefficients assigned to each block of the at least one region.

Abstract: A control system for an electromechanical-braking system provided with actuator elements configured to actuate braking elements for exerting a braking action has a control stage for controlling the braking action on the basis of a braking reference signal. The control stage comprises a model-based predictive control block, in particular of a generalized predictive self-adaptive control type, operating on the basis of a control quantity representing the braking action. The control system further has: a model-identification stage, which determines parameters identifying a transfer function of the electromechanical-braking system; and a regulation stage, which determines an optimal value of endogenous parameters of the control system on the basis of the value of the identifying parameters.

Abstract: The present disclosure relates to a method for locating the iris in an image of an eye, comprising steps of locating the pupil in the image, of detecting positions of intensity steps of pixels located on a line passing through the pupil and transition zones between the iris and the cornea, on either side of the pupil, and of determining the center and the radius of a circle passing through the detected positions of the transitions.

Abstract: An analog-to-digital converter device may include an input multiplexer circuit having analog input terminals configured to receive a respective plurality of analog input signals. The input multiplexer circuit may be responsive to a first select input. The device may also include a trigger multiplexer circuit having input terminals configured to receive respective triggering signals. The trigger multiplexer circuit may be responsive to a second select input. Analog-to-digital converter circuitry may be configured to convert the selected analog signal into a digital signal. A sequence arbiter may be coupled to the first and second select inputs and may have input terminals configured to receive a respective plurality of conversion sequence configuration signals. The sequence arbiter may be configured to manage each conversion sequence of the analog-to-digital converter circuitry based upon the relative conversion sequence configuration signal received, and control the conversion sequences.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Abstract: This invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and in particular to a method of addressing zero-delay frequency switching for cognitive dynamic frequency hopping. The method combines regular (periodic) channel maintenance with dynamic frequency hopping over a cluster of vacated channels that are initially setup such that the switching delays for channel setup and channel availability check are eliminated.