Abstract: A microfluidic system through which a solution of at least an oxidable compound is fed to a feed manifold of an energy converting electrochemical device includes a flow connector. The flow connector includes a silicon platform having a bottom side and an opposing top side, and through holes extending therethough. The silicon platform includes first and second channels defined on the bottom side for communicating with the through holes. The second channel forms an inlet for the feed manifold of the energy converting electrochemical device when the bottom side of the silicon platform is coupled to a flat coupling area of the device. A micropump module is coupled to the top side of the silicon platform for communicating with the through holes in the first and second channels. First and second supply cartridges are coupled to the top side of the silicon platform for communicating with the through holes in the first channel.
Type:
Grant
Filed:
January 2, 2007
Date of Patent:
December 25, 2012
Assignee:
STMicroelectronics S.R.L.
Inventors:
Giuseppe Emanuele Spoto, Roberta Giuffrida, Salvatore Leonardi, Salvatore Abbisso
Abstract: A detector array for an imaging system may exploit the different sensitivities of array pixels to an incident flux of low energy photons with a wavelength falling near the high end of the range of sensitivity of the semiconductor. The detector array may provide the de-multiplexable spatial information. The detector array may include a two-terminal multi-pixel array of Schottky photodiodes electrically connected in parallel.
Abstract: A method for monitoring the execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes. Current cumulative signatures are produced using deterministic address, control or data logic signals involved in the execution of the sequence and taken off at various points of the integrated circuit. A final cumulative signature is compared with an expected signature and an error signal is produced if the two signatures are not identical. Particularly useful to secure integrated circuits for smart cards.
Abstract: A method of decoding a received systematic code encoded block corresponding to an original block of information, wherein the received systematic code encoded block may include soft systematic values, may include detecting an error condition in the received systematic code encoded block. The method may also include decoding the received systematic code encoded block for retrieving the original block of information if the error condition in the received systematic code encoded block is detected and processing the soft systematic values to retrieve the original block of information instead of the decoding if the error condition in the received systematic code encoded block is not detected.
Type:
Grant
Filed:
November 26, 2008
Date of Patent:
December 25, 2012
Assignee:
STMicroelectronics N.V.
Inventors:
Friedbert Berens, Cem Derdiyok, Franck Kienle, Timo Lehnigk-Emden, Norbert Wehn
Abstract: A method for long impulse response digital filtering of an input data stream, by use of a digital filtering system. Where the input data stream is divided into zero-input signals and zero-state signals. One of the zero-input signals and a corresponding impulse response of the digital filtering system is converted to the frequency domain to determine a respective zero-input response of the digital filtering system. One of the zero-state signals is convolved with a corresponding impulse response of the digital filtering system to determine a respective zero-state response of the digital filtering system, wherein at least part of the zero-input signal precedes the zero-state signal. The zero-state response of the digital filtering system is added to the zero-input response of the digital filtering system to determine the response of the digital filtering system. Apparatus for effecting this method is also disclosed.
Type:
Grant
Filed:
November 19, 2007
Date of Patent:
December 25, 2012
Assignee:
STMicroelectronics Asia Pacific Pte Ltd.
Abstract: A resonant power converter for ultra-efficient radio frequency transmission and associated methods. In one exemplary embodiment, the invention is digitally actuated and uses a combination of a noise-shaped encoder, a charging switch, and a high-Q resonator coupled to an output load, typically an antenna or transmission line. Energy is built up in the electric and magnetic fields of the resonator, which, in turn, delivers power to the load with very little wasted energy in the process. No active power amplifier is required. The apparatus can be used in literally any RF signal application (wireless or otherwise), including for example cellular handsets, local- or wide-area network transmitters, or even radio base-stations.
Type:
Grant
Filed:
April 4, 2011
Date of Patent:
December 25, 2012
Assignee:
STMicroelectronics N.V.
Inventors:
Steven R. Norsworthy, Ross W. Norsworthy
Abstract: A system and method for processing a wafer includes a charge neutralization system. The wafer processing system includes a wafer measuring device that can measure characteristics of a surface of the semiconductor wafer. One or more wafer processing stations perform a chemical mechanical polish (CMP) process on the wafer surface. A desica cleaning station can clean and dry the semiconductor wafer. The wafer processing system further includes a charge neutralizing device that can alter a surface charge of the wafer surface.
Abstract: A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase.
Abstract: A voltage-controlled vertical bi-directional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well in which is formed a MOS transistor, the first P-type well and the gate of the MOS transistor being connected to a control terminal, said N-type region being connected to a main terminal of the MOS transistor, and the second main terminal of the MOS transistor being connected to the rear surface voltage of the switch.
Abstract: A method of playing a compressed digital video sequence, comprising steps comprising attributing to each frame a display duration determined as a function of a playing speed set point, and at each period of a frame synchronization signal: if a display duration cumulative value is equal to or greater than a threshold value corresponding to the period of the synchronization signal, playing a previously acquired decoded frame and decreasing the cumulative value of the threshold value; and if the present cumulative value is less than the threshold value, acquiring a new decoded frame and adding the display duration attributed to the newly acquired frame to the cumulative value, until the cumulative value is equal to or greater than the threshold value, playing a last decoded frame acquired and decreasing the cumulative value of the threshold value.
Type:
Grant
Filed:
November 17, 2010
Date of Patent:
December 25, 2012
Assignee:
STMicroelectronics (Grenoble 2) SAS
Inventors:
Roland Bohrer, Roselyne Haller, Sebastien Leblanc
Abstract: A method and a circuit for controlling a power recovery stage of a plasma display panel including a resonant circuit of at least one inductive element and one capacitive element, wherein the capacitive element is precharged to half a supply voltage of the display panel.
Abstract: A sector of an electrically programmable non-volatile memory includes memory cells connected to word lines and to bit lines, each cell including at least one transistor having a gate connected to a word line, a drain connected to a bit line and a source connected to a source line. The sector includes at least two distinct wells insulated from one another, each including a number of cells of the sector, being able to take different potentials, and in that the sector has at least one bit line electrically linked to the drain of at least two cells mounted on two distinct wells.
Abstract: A link device for three-dimensional integrated structure may include a module having a first end face designed to be in front of a first element of the structure, and a second end face designed to be placed in front of a second element of the structure. The two end faces may be substantially parallel, and the module including a substrate having a face substantially perpendicular to the two end faces and carrying an electrically conducting pattern formed in a metallization level on top of the face and enclosed in an insulating region. The electrically conducting pattern may include a first end part emerging onto the first end face and a second end part emerging onto the second end face and connected to the first end part.
Type:
Application
Filed:
June 14, 2012
Publication date:
December 20, 2012
Applicant:
STMicroelectronics SA
Inventors:
Pierre Bar, Sylvain Joblot, Jean-Francois Carpentier
Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.
Type:
Application
Filed:
June 13, 2012
Publication date:
December 20, 2012
Applicant:
STMicroelectronics (Crolles 2) SAS
Inventors:
Grégory Bidal, Laurent Favennec, Raul Andres Bianchi
Abstract: An integrated circuit chip including a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type, and a device of protection against attacks including: between the wells, trenches with insulated walls filled with a conductive material, said trenches extending from the upper surface of the wells to the substrate; and a circuit capable of detecting a modification of the stray capacitance formed between said conductive material and a region of the chip.
Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.
Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
Type:
Grant
Filed:
June 1, 2010
Date of Patent:
December 18, 2012
Assignee:
STMicroelectronics S.r.l.
Inventors:
Flavio Villa, Gabriele Barlocchi, Pietro Corona
Abstract: MOS device formed in a semiconductor body having a first conductivity type and a surface and housing a first current-conduction region and a second current-conduction region, of a second conductivity type. The first and second current-conduction regions define between them a channel, arranged below a gate region, formed on top of the surface and electrically insulated from the channel region. A conductive region extends on top of a portion of the channel, adjacent to and insulated from the gate region only on a side thereof facing the first current-conduction region. The conductive region is biased so as to modulate the current flowing in the channel.
Type:
Grant
Filed:
June 13, 2007
Date of Patent:
December 18, 2012
Assignee:
STMicroelectronics S.r.l.
Inventors:
Salvatore Cascino, Maria Concetta Nicotra, Antonello Santangelo
Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.
Type:
Application
Filed:
June 12, 2012
Publication date:
December 13, 2012
Applicants:
International Business Machines, STMicroelectronics, Inc.
Inventors:
John H. ZHANG, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
Abstract: The disclosure relates to a method of manufacturing vibratory elements, comprising forming on a substrate a multilayer structure by an integrated circuit manufacturing method, the multilayer structure comprising an element susceptible of vibrating when it is subjected to an electrical signal, and electrodes for transmitting an electrical signal to the vibratory element, the vibratory element comprising a mechanical coupling face that is able to transmit to control element vibrations perceptible by a user.
Type:
Application
Filed:
June 6, 2012
Publication date:
December 13, 2012
Applicants:
STMicroelectronics (Grenoble 2) SAS, STMicroelectronics SA