Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.

Abstract: An integrated microelectromechanical structure is provided with a driving mass, anchored to a substrate via elastic anchorage elements and designed to be actuated in a plane with a driving movement; and a first sensing mass and a second sensing mass, suspended within, and coupled to, the driving mass via respective elastic supporting elements so as to be fixed with respect thereto in said driving movement and to perform a respective detection movement in response to an angular velocity. In particular, the first and the second sensing masses are connected together via elastic coupling elements, configured to couple their modes of vibration.

Abstract: Embodiments described in the present disclosure relate to a method for initializing registers of peripherals of a microcontroller, including acts of: accessing initialization data in a non-volatile memory connected by a main bus to a processing unit of the microcontroller and to the peripherals, activating a peripheral including registers to be initialized, and transferring the data read into the registers of the activated peripheral, the initialization data being accessed in the memory by an initialization circuit distinct from the processing unit, the initialization data accessed being sent to the peripherals by an initialization bus distinct from the main bus.

Abstract: A device for controlling an image sensor including at least one photosensitive cell including a photodiode capable of discharging into a sense node via a first MOS transistor, the sense node being connected to the gate of a second MOS transistor having its source connected to a processing system. The device includes a bias circuit capable of increasing the voltage of the source during the discharge of the photodiode into the sense node.

Abstract: A method for providing a priority-based, low-collision distributed coordination function (DCF) in a wireless network is provided. The network includes an access point and a plurality of stations. The method includes receiving at a first station a super-frame from the access point. The super-frame is operable to define a service period for each of the stations. A priority for the first station is determined based on the super-frame. A back-off time is selected for the first station based on the priority.

Abstract: The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of the supply voltage or by the intermediary of a reception or emission terminal of a data or clock signal. Applicable in particular to electronic tags comprising a reduced number of interconnection terminals.

Abstract: The system and method are for efficient detection and restoration of data storage array defects. The system may include a data storage subsystem, wherein the data storage subsystem includes a data storage array, read-write logic coupled to the data storage array, a parity generator for producing and storing check data during write operations to the data storage array and generating check data during read operations on the data storage array, and a parity checker for verifying the stored check data with generated check data and identifying defective data read-write elements during read operations on the data storage array. The subsystem may further include a Built-in Self Test (BIST) generator operating only on the identified defective data read-write elements for determining defective data storage elements in the defective data read-write elements, and a restoration mechanism for restoring the valid operation of data access elements containing the defective data storage elements in the data storage array.

Abstract: Three alternative methods of controlling transmit power in a basic service set (BSS) including a plurality of stations that have successfully synchronized with an access point include providing each BSS with one transmit power limit that is not more than the lowest one of the transmit power limits of all of its operating channels, providing each BSS with one transmit power limit that is fixed for physical layer convergence procedure (PLCP) protocol data units (PPDU) with each channel bandwidth, or providing each BSS with one transmit power limit that is fixed for each 80 MHz channel.

Abstract: The present disclosure provides a digital audio signal processing system that comprises a set of delay lines, allpass and lowpass filters to achieve the reverberation effect. The present disclosure further provides a method for generating and controlling digital reverberations for audio signals. The reverberation generated will have an increasing echo density in the time domain and a faster decay of high frequency signals than low frequency signals. The controlling mechanism of reverberation generation is realized through the extraction of the real environment characteristics.

Abstract: The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor.

Abstract: A method is for transferring data from a source target to a destination target in a network. The method includes sending at least one request packet for the destination target, with the request packet containing information relating to a first address where data are located and a second address where data are to be stored. Moreover, at least one transaction request is sent to the source target, with the read request being elaborated from information contained in the request packet. The source target transfers the data located at the first address to the second address.

Abstract: In a PBSS cluster environment, the beacon interval is allocated such that each PBSS in a PBSS cluster possesses its own master sub-beacon interval. Moreover, each member of the PBSS cluster can share unoccupied sub-beacon intervals. When a master PBSS fails to use its own master sub-beacon interval or the beacon intervals which are unoccupied, the available idle time within the beacon interval can be utilized by other member PBSSs in the PBSS cluster. As available or idle beacon interval time is allocated, each master PBSS retains the highest priority to its own master sub-beacon interval thus providing immediate access to a beacon interval when necessary.

Abstract: Described herein are techniques for forming, during wafer processing, a conductive shielding layer for a chip formed from a wafer. The conductive shielding layer can be formed on multiple sides of a chip prior to dicing the wafer to separate the chip from the wafer. A wafer may be processed to form trenches that extend substantially through the wafer. The trenches may be formed opposite scribe lines that identify boundaries between chips of the wafer and may extend through the wafer toward the scribe lines. A shielding layer may be formed along the trenches.

Abstract: A method (200a-200b), apparatus (104), and computer program for detecting sequences of digitally modulated symbols transmitted by multiple sources (102, 102a-102t) are provided. A real-domain representation that separately treats in-phase and quadrature components of a received vector, channel gains, and a transmitted vector transmitted by the multiple sources (102, 102a-102t) is determined. The real-domain representation is processed to obtain a triangular matrix. In addition, at least one of the following is performed: (i) hard decision detection of a transmitted sequence and demapping of corresponding bits based on a reduced complexity search of a number of transmit sequences, and (ii) generation of bit soft-output values based on the reduced complexity search of the number of transmit sequences. The reduced complexity search is based on the triangular matrix.

Abstract: A via connecting the front surface of a substrate to its rear surface, this substrate including a porous region extending from at least a portion of the periphery of the via, the via including outgrowths extending in pores of the porous region.

Abstract: An authentication method of a first module by a second module includes the steps of generating a first random datum by the second module to be sent to the first module, generating a first number by the first module starting from the first datum and by way of a private key, and generating a second number by the second module to be compared with the first number, so as to authenticate the first module. The step of generating the second number is performed starting from public parameters and is independent of the step of generating the first number.

Abstract: A stepwise voltage ramp generator includes a tank capacitor, a terminal of which is coupled to a reference potential to be charged with a voltage ramp. A transistor couples the tank capacitor to a supply line. A diode-connected transistor, biased with a bias current is coupled to the transistor to form a current mirror. A by-pass switch is electrically coupled in parallel to the diode-connected transistor, and is controlled by a PWM timing signal, the duty-cycle of which determines a mean slope of the generated voltage ramp.

Abstract: An integrated microelectromechanical structure is provided with a driving mass, anchored to a substrate via elastic anchorage elements and designed to be actuated in a plane with a driving movement; and a first sensing mass and a second sensing mass, suspended within, and coupled to, the driving mass via respective elastic supporting elements so as to be fixed with respect thereto in said driving movement and to perform a respective detection movement in response to an angular velocity. In particular, the first and the second sensing masses are connected together via elastic coupling elements, configured to couple their modes of vibration.

Abstract: An electronic device includes a capacitive component with variable capacitance coupled to a control stage that controls the capacitance based on a reference signal, with a reference frequency, and an excitation signal, that is a multiple of the reference frequency. The capacitive component includes a variable capacitive network having a plurality of switched capacitors, each being switchable between a first configuration, where it is connected between connection terminals of the capacitive component, and a second configuration, where it is connected at most to one of the connection terminals. The control stage includes a logic module, coupled to the variable capacitive network for switching periodically each capacitor between the first configuration and the second configuration. A sign circuit, coupled to the capacitive component supplies a control signal having edges concordant with the excitation signal in one half-period of each cycle of the reference signal and discordant edges in the other half-period.

Abstract: A circuit includes a differential amplifier having a folded cascode architecture with a pair of cascode transistors. A sensing circuit senses a common mode input voltage of a differential input signal applied to the differential amplifier. A bias generator circuit generates a bias voltage for application to the pair of cascode transistors in the folded cascode architecture. The bias generator circuit is connected to an output of the sensing circuit such that the generated bias voltage has a value which is dependent on the sensed common mode input voltage. This dependence stabilizes a common mode output voltage from the differential amplifier in response to changes in the common mode input voltage.