Abstract: A LIN receiver circuit includes filtering circuitry receiving an input signal and producing a filtered signal, a first comparator comparing the filtered signal to a threshold voltage, and a driver block producing the receiver output signal. The receiver circuit further includes an input comparator, signal-adjusting circuitry, and deglitching circuitry. The input comparator detects a low voltage on the input signal, and the signal-adjusting circuitry drives the filtered signal to a particular value to shorten the length of a glitch at the output of the first comparator. Meanwhile, the deglitching circuitry detects and removes the glitch to produce a deglitcher output signal. The deglitcher output signal is received by the driver block, which outputs the receiver output signal, wherein the receiver output signal contains no glitches, and is delayed by no more than 7.5 ?s, thus providing immunity to ISO pulses.

Abstract: A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.

Abstract: A device includes a first switch and a second switch, each switch being integrated on a chip having a back surface and an opposite front surface. Each chip includes a first conduction terminal and a control terminal on the front surface, while a second conduction terminal of the switch is located on the back surface. The first switch and the second switch are connected in a half-bridge configuration with the first switch's second conduction terminal electrically connected to the second switch's first conduction terminal. The chips are installed in a common package comprising an insulating body with an embedded heat sink. The chips of the switches are mounted on the heat sink such that the second conduction terminal of the first switch and the first conduction terminal of the second switch are in contact with the heat sink, with the heat sink providing the electrical connection between the two switches.

Abstract: A countermeasure in a logic circuit having a logic gate supplying a binary output signal, the method including supplying binary data having random values to inputs of logic circuit during a precharge phase; supplying data to process to inputs of the logic circuit during a data processing phase; supplying on input of the logic circuit a precharge command signal launching a precharge phase; and under the effect of the precharge command signal, adapting the functioning of a logic gate of the logic circuit, statistically unbalanced, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase.

Abstract: Embodiments described in the present disclosure relate to a method of processing faults in a control unit, the method including: upon each request for reading a datum in a first memory, received by a first interface circuit for accessing the first memory, calculating by means of the first interface circuit, a check word based on the datum read, if the check word calculated is different from a check word read in the memory in association with the datum read, activating an error signal by means of the first interface circuit, and sending the error signal to an output circuit of the control unit, without using any circuits of the control unit, likely to send a request to access the first memory.

Abstract: First and second electronic devices each include an insulating package embedding a chip of semiconductor material which integrates at least one electronic component. Each insulating package has a mounting surface for mounting the respective electronic device on a substrate and an opposite free surface. A heatsink is fixed to the free surfaces through respective first and second base portions. A connection element is configured to connect the first base portion to the second base portion. The heatsink also includes, for each electronic device, at least one stabilizing element extending from the respective base portion to make contact with a substrate to which the mounting surfaces of the first and second electronic devices are attached.

Abstract: A heat spreader is provided for use with a thermally enhanced flip-chip ball grid array package. In the package, a semiconductor die is positioned front-side down on a package substrate, coupled thereto via solder balls. Passive devices can also be coupled to the substrate alongside the die. The heat spreader is positioned over the substrate and die, in thermal contact with the die. A projection in the center of the heat spreader makes contact with the back surface of the die via a thermal interface material, to draw heat from the die for improved cooling. The projection enables close contact with a thinned die while accommodating thicker passive devices positioned around the die on the substrate.

Abstract: A process manufactures an interaction structure for a storage medium. The process includes forming a first interaction head provided with a first conductive region having a sub-lithographic dimension. The step of forming a first interaction head includes: forming on a surface a first delimitation region having a side wall; depositing a conductive portion having a deposition thickness substantially matching the sub-lithographic dimension on the side wall; and then defining the conductive portion. The sub-lithographic dimension preferably is between 1 and 50 nm, more preferably 20 nm.

Abstract: An electronic device includes a first and second integrated chip switch, each having a back (drain) surface and an opposite front (source) surface. An insulating package embeds the switches along with first, second and third heat sinks. The front surface of the first switch and back surface of the second switch are mounted to the first heat sink to couple first switch source to the second switch drain through the first heat sink in a half-bridge configuration. The first switch back surface is mounted to the second heat sink and the second switch front surface is mounted to the third heat sink. The package includes first, second and third openings which expose, respectively, the first, second and third heat sinks. The first heat sink opening is provided on one surface of the package, while the second and third heat sink openings are provided on an opposite surface of the package.

Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.

Abstract: An embodiment of a pre-emphasis circuit, an embodiment of a method for pre-emphasizing complementary single-ended signals, an embodiment of a transmitter, and an embodiment of a communication system.

Abstract: An insulating body embeds an integrated circuit and has a mounting surface, an opposite free surface, and at least one pin exposed along an edge of the mounting surface and electrically connected to a terminal of the integrated circuit. A heatsink configured to dissipate heat produced by the integrated circuit is provided in correspondence of the free surface. The heatsink includes at least one protruding element including a connection portion partly extending in contact with the free surface and partly protruding beyond a boundary of the free surface (the connection portion having a free end being distal from the insulating body), and a mounting portion extending from the free end at least up to a plane of the mounting surface. The heatsink is further electrically connected to a terminal of the integrated circuit chip. The protruding element is placed in correspondence of the at least one pin.

Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.

Abstract: On embodiment is directed to a welding pad capable of receiving a ball-shaped copper wire at its end, including a first copper pad coated with a protection layer and topped with a second pad containing aluminum having dimensions smaller than those of the first pad and smaller than the ball diameter once said ball has been welded to the welding pad.

Abstract: A semiconductor device includes: a semiconductor body; a trench having side walls and a bottom; a gate region made of conductive material, extending within the trench; an insulating region, extending along bottom portions of the side walls of the trench and on the bottom of the trench; a gate insulating layer, extending along top portions of the side walls of the trench, laterally with respect to the gate region; a conductive region, extending within the trench, surrounded at the top and laterally by the gate region and surrounded at the bottom and laterally by the insulating region; and a field insulating layer, arranged between the gate region and the conductive region. The gate insulating layer includes thickened portions, each of which contacts the insulating region and has a thickness that increases as the depth increases.

Abstract: An integrated circuit (IC) provides a reset function. The IC receives a command that is defined by a first sequence of counts of signal transitions of a first signal during windows of a second signal and provides a reset function when it is determined that the command is received. A device including the IC and a system including the device are provided.

Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.

Abstract: An approach for executing a toolkit action in an IC card includes storing in the IC card one or more identifiers and corresponding toolkit actions, and passing a web page in input to a converter in the IC card. The converter is configured to identify one or more of the identifiers in the html page and related text information associated with the identifiers. The approach includes sending the toolkit actions corresponding to the identifiers identified and the related text information to an application SIM Application Toolkit (SAT) of the IC card, for displaying the text information of the web page as SIM Application Toolkit menu.

Abstract: An LIN transmitter includes a current mirror coupled to a transmit output node and a control circuit coupled to a transmit input node for controlling the current mirror with various load current control signals.

Abstract: A regulator structure includes a first differential amplifier having a first input coupled to a reference voltage node. A second differential amplifier has a first input coupled to the output of the first differential amplifier. A third differential amplifier has a first input coupled to the output of the first differential amplifier. A first pmos transistor has its gate coupled to the second differential amplifier output, and its drain coupled to a second input of each of the first and second differential amplifiers. A second pmos transistor has its gate coupled to the third differential amplifier output, and its drain configured to output a regulated voltage which is also a second input of the third differential amplifier. A circuit is configured to replicate the regulated voltage and couple the replicated regulated voltage to the drain of the first pmos transistor.