Abstract: A control device for a resonant converter is described. The converter comprises a switching circuit adapted to drive a resonant circuit that includes at least one capacitor. The converter is adapted to convert an input signal into an output signal and the switching circuit includes at least a half bridge of first and second switches, the central point of said half bridge being connected to the resonant circuit. The control device comprises a controller adapted to generate at least a control signal of the switching circuit by comparing a signal representative of the energy of the resonant circuit with at least another signal.

Abstract: A method for searching a digital transmission having unknown carrier and symbol frequencies in a modulated reception signal, includes performing successive trials of several carrier and symbol frequencies, using decreasing values of the symbol frequency, demodulating the reception signal with the tried carrier frequency, filtering the demodulated signal in a band having a width corresponding to the currently tried symbol frequency, and producing samples of the filtered signal. For each currently tried symbol frequency, forming a complex indicator having a real component and an imaginary component established from the successive samples of the filtered signal such that they have cyclostationary properties and that one of the components tends to cancel when the other component tends towards a relative maximum, building the spectrum of the variation of the complex indicator, searching for a singular spike in the spectrum, and determining the real symbol frequency from the frequency of the spike.

Abstract: A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase.

Abstract: A method of power point tracking for operating a photovoltaic power plant, which includes a DC-DC converter of the output voltage of a panel having a power switch driven by a PWM control signal of variable duty-cycle generated by a PWM control circuit, in discontinuous conduction mode or continuous conduction mode depending on the current load of the converter, is implemented by low cost analog circuits. The method does not require the use of any analog-to-digital conversion, digital processing or storage resources and may use a single voltage sensor.

Abstract: A method of decoding a received systematic code encoded block corresponding to an original block of information, wherein the received systematic code encoded block may include soft systematic values, may include detecting an error condition in the received systematic code encoded block. The method may also include decoding the received systematic code encoded block for retrieving the original block of information if the error condition in the received systematic code encoded block is detected and processing the soft systematic values to retrieve the original block of information instead of the decoding if the error condition in the received systematic code encoded block is not detected.

Abstract: A method for monitoring the execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes. Current cumulative signatures are produced using deterministic address, control or data logic signals involved in the execution of the sequence and taken off at various points of the integrated circuit. A final cumulative signature is compared with an expected signature and an error signal is produced if the two signatures are not identical. Particularly useful to secure integrated circuits for smart cards.

Abstract: A system and method for processing a wafer includes a charge neutralization system. The wafer processing system includes a wafer measuring device that can measure characteristics of a surface of the semiconductor wafer. One or more wafer processing stations perform a chemical mechanical polish (CMP) process on the wafer surface. A desica cleaning station can clean and dry the semiconductor wafer. The wafer processing system further includes a charge neutralizing device that can alter a surface charge of the wafer surface.

Abstract: The method includes an interference deduction mode for reducing interferences between a wideband device and a narrowband device. The method is performed within the wideband device and includes detecting an emission from and/or a reception performed by the narrowband device; determining from the detection step a group of at least one sub-carrier having frequencies interfering with the narrowband devices; and frequency shifting at least a part of frequency band of the wideband device including the group of at least one interfering sub-carriers with a chosen frequency shift such that at least a part of frequency band of the narrowband device is excluded from the frequency band of the wideband device.

Abstract: A microfluidic system through which a solution of at least an oxidable compound is fed to a feed manifold of an energy converting electrochemical device includes a flow connector. The flow connector includes a silicon platform having a bottom side and an opposing top side, and through holes extending therethough. The silicon platform includes first and second channels defined on the bottom side for communicating with the through holes. The second channel forms an inlet for the feed manifold of the energy converting electrochemical device when the bottom side of the silicon platform is coupled to a flat coupling area of the device. A micropump module is coupled to the top side of the silicon platform for communicating with the through holes in the first and second channels. First and second supply cartridges are coupled to the top side of the silicon platform for communicating with the through holes in the first channel.

Abstract: A detector array for an imaging system may exploit the different sensitivities of array pixels to an incident flux of low energy photons with a wavelength falling near the high end of the range of sensitivity of the semiconductor. The detector array may provide the de-multiplexable spatial information. The detector array may include a two-terminal multi-pixel array of Schottky photodiodes electrically connected in parallel.

Abstract: A voltage-controlled vertical bi-directional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well in which is formed a MOS transistor, the first P-type well and the gate of the MOS transistor being connected to a control terminal, said N-type region being connected to a main terminal of the MOS transistor, and the second main terminal of the MOS transistor being connected to the rear surface voltage of the switch.

Abstract: A resonant power converter for ultra-efficient radio frequency transmission and associated methods. In one exemplary embodiment, the invention is digitally actuated and uses a combination of a noise-shaped encoder, a charging switch, and a high-Q resonator coupled to an output load, typically an antenna or transmission line. Energy is built up in the electric and magnetic fields of the resonator, which, in turn, delivers power to the load with very little wasted energy in the process. No active power amplifier is required. The apparatus can be used in literally any RF signal application (wireless or otherwise), including for example cellular handsets, local- or wide-area network transmitters, or even radio base-stations.

Abstract: A method of playing a compressed digital video sequence, comprising steps comprising attributing to each frame a display duration determined as a function of a playing speed set point, and at each period of a frame synchronization signal: if a display duration cumulative value is equal to or greater than a threshold value corresponding to the period of the synchronization signal, playing a previously acquired decoded frame and decreasing the cumulative value of the threshold value; and if the present cumulative value is less than the threshold value, acquiring a new decoded frame and adding the display duration attributed to the newly acquired frame to the cumulative value, until the cumulative value is equal to or greater than the threshold value, playing a last decoded frame acquired and decreasing the cumulative value of the threshold value.

Abstract: An embodiment for manufacturing an electronic circuit forms at least one first structure on a semiconductor substrate, determines at least one electrically defined characteristic of the at least one first structure, selects a reticle corresponding to the measured characteristic, and forms at least one additional structure on the semiconductor substrate with the selected reticle.

Abstract: A method for long impulse response digital filtering of an input data stream, by use of a digital filtering system. Where the input data stream is divided into zero-input signals and zero-state signals. One of the zero-input signals and a corresponding impulse response of the digital filtering system is converted to the frequency domain to determine a respective zero-input response of the digital filtering system. One of the zero-state signals is convolved with a corresponding impulse response of the digital filtering system to determine a respective zero-state response of the digital filtering system, wherein at least part of the zero-input signal precedes the zero-state signal. The zero-state response of the digital filtering system is added to the zero-input response of the digital filtering system to determine the response of the digital filtering system. Apparatus for effecting this method is also disclosed.

Abstract: A method and a circuit for controlling a power recovery stage of a plasma display panel including a resonant circuit of at least one inductive element and one capacitive element, wherein the capacitive element is precharged to half a supply voltage of the display panel.

Abstract: A semiconductor package includes a substrate, a stiffener ring coupled to the substrate and configured to form a well with the substrate, and a die positioned in the well. A thermal interface is positioned on the die. A heat spreader is coupled to the stiffener ring so that a portion of the heat spreader is positioned in the well and the thermal interface thermally couples the heat spreader to the die. The portion of the heat spreader positioned in the well adds rigidity to the semiconductor package and facilitates the use of thin dies.

Abstract: A device and method to compensate for distortions of amplitude that afflict systems for communicating through capacitive coupling. A circuit includes a first transmitter stage, a first receiver stage, and a first coupling capacitor, coupled between the first transmitter stage and the first receiver stage. The first receiver stage includes a calibration amplifier of a variable-gain type coupled between the first coupling capacitor and an output of the electronic circuit. The electronic circuit includes a reference channel formed by: a transmission calibration stage; a reception calibration stage; and a reference capacitor coupled between the transmission calibration stage and the reception calibration stage.

Abstract: A method of controlling an electronic charge retention circuit for time measurement, including at least a first capacitive element, the dielectric of which has a leakage, and at least a second capacitive element, the dielectric of which has a higher capacitance than the first, the two elements having a common electrode defining a floating node that can be connected to an element for measuring its residual charge, in which a charge retention period is programmed or initialized by injecting or extracting charges via the first element.

Abstract: An integrated circuit chip includes: a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type; in each well of the first type, a plurality of MOS transistors having a channel of the second conductivity type, and in each well of the second type, a plurality of MOS transistors having a channel of the first type, transistors of neighboring wells being inverted-connected; and a device of protection against attacks, including: a layer of the second type extending under said plurality of wells, from the lower surface of said wells; and regions of lateral insulation between the wells, said regions extending from the upper surface of the wells to said layer.