Abstract: A control system for an electromechanical-braking system provided with actuator elements configured to actuate braking elements for exerting a braking action has a control stage for controlling the braking action on the basis of a braking reference signal. The control stage comprises a model-based predictive control block, in particular of a generalized predictive self-adaptive control type, operating on the basis of a control quantity representing the braking action. The control system further has: a model-identification stage, which determines parameters identifying a transfer function of the electromechanical-braking system; and a regulation stage, which determines an optimal value of endogenous parameters of the control system on the basis of the value of the identifying parameters.

Abstract: A startup circuitry connected to a main circuit which has at least an output terminal connected to its feedback terminal by a feedback loop. The startup circuitry is connected to the main circuit in such a manner to break the feedback loop, by having a first circuit node connected to said output terminal of said main circuit and a second circuit node connected to its feedback terminal, said startup circuitry providing a correct output voltage value during the startup phase of said main circuit.

Abstract: A process for manufacturing a MOS device includes forming a semiconductor layer having a first type of conductivity; forming an insulated gate structure having an electrode region, above the semiconductor layer; forming body regions having a second type of conductivity, within the semiconductor layer, laterally and partially underneath the insulated gate structure; forming source regions having the first type of conductivity, within the body regions; and forming a first enrichment region, in a surface portion of the semiconductor layer underneath the insulated gate structure. The first enrichment region has the first type of conductivity and is set at a distance from the body regions. In order to form the first enrichment region, a first enrichment window is defined within the insulated gate structure, and first dopant species of the first type of conductivity are introduced through the first enrichment window and in a way self-aligned thereto.

Abstract: A surface of a support comprising through micropassages is brought into contact with an aqueous solution comprising a plurality of particles in suspension and a pad. A pressure perpendicular to the plane of the support, between the pad and the surface of the support, and a relative movement of the pad and of the surface in a direction parallel to the plane of the support are applied. At least one particle is thus introduced in each microgap to form a porous material therein.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Abstract: An embodiment of a transmitter includes detection, generating, and transmission stages. The detection stage is configured to detect a first signal having a first component that includes a frequency, and the generating stage is configured to generate a data component that includes approximately the frequency in response to the detection of the first signal. The transmission stage is configured to transmit a second signal having the data component while the detection stage is detecting the first signal. For example, two or more such transmitters (e.g., two or more smart phones) may simultaneously transmit OFDM signals on the same subcarrier frequencies and over the same channel space. By allowing the simultaneous transmission of multiple signals on the same frequencies and over the same channel space, such a transmitter may increase the effective bandwidth of the channel space, and thus may allow more devices to simultaneously share the same channel space.

Abstract: A driving circuit has output terminal connected to an ultrasonic transducer and provides an output voltage. The driving circuit includes an output transistor coupled between a voltage reference and the output terminal, a high voltage comparator coupled to said output terminal and to a threshold voltage reference), a start-up circuit controlled by a setting signal; and a switching ON/OFF circuit having an input coupled to the start-up circuit an input coupled to the comparator, and an output coupled to a control terminal of the output transistor. The start-up circuit provides an ON signal to the switching on/off circuit and the comparator provides an OFF signal to the switching on/off circuit which switches off the output transistor. The high voltage comparator generates the switching off signal in response to the output voltage reaching a desired supply voltage value which depends on the value of the first threshold voltage reference.

Abstract: A restoring operation of a storage device based on a flash memory. In an embodiment, a storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A method may detect a plurality of conflicting physical blocks for a corrupted logical block and determines a plurality of validity indexes. One or more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded.

Abstract: A system for exchanging information in an on-chip communication network using optical flow information for communication between Intellectual Property cores. The information is exchanged between a plurality of initiators and targets in the Intellectual Property cores. The system includes a router for propagating optical flow information from the initiators to the targets. Each initiator includes an interface to convert the traffic generated by the initiator and transmit it in the form of an optical flow within the on-chip communication network, and each target includes an interface to convert information from the optical form into the electrical form. The system is organized as a parametric system and includes programming module to define a first set of high level parameters, a second set of initiator network interface parameters and a third set of target network interface parameters.

Abstract: An ITO sensor design and method for making the same is optimized to minimize noise from an LCD. The design includes a two layer sensor design having a transmitter line (Tx) placed in a first layer and a receiver line (Rx) placed in a second layer in a diamond-shaped pattern. The diamond shape maximizes the sensitivity of the sensor.

Abstract: This invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and in particular to a method of addressing zero-delay frequency switching for cognitive dynamic frequency hopping. The method combines regular (periodic) channel maintenance with dynamic frequency hopping over a cluster of vacated channels that are initially setup such that the switching delays for channel setup and channel availability check are eliminated.

Abstract: An analog-to-digital converter device may include an input multiplexer circuit having analog input terminals configured to receive a respective plurality of analog input signals. The input multiplexer circuit may be responsive to a first select input. The device may also include a trigger multiplexer circuit having input terminals configured to receive respective triggering signals. The trigger multiplexer circuit may be responsive to a second select input. Analog-to-digital converter circuitry may be configured to convert the selected analog signal into a digital signal. A sequence arbiter may be coupled to the first and second select inputs and may have input terminals configured to receive a respective plurality of conversion sequence configuration signals. The sequence arbiter may be configured to manage each conversion sequence of the analog-to-digital converter circuitry based upon the relative conversion sequence configuration signal received, and control the conversion sequences.

Abstract: A buffer circuit includes a biasing circuit operable to generate first and second biasing signals. A capacitive network includes an input adapted to receive an input signal and the capacitive network is operable responsive to the input signal to generate first and second bootstrapped signals. A push-pull stage includes first and second control inputs and an output. The push-pull stage is coupled to the biasing circuit to receive the first and second biasing signals on the first and second control inputs, respectively, and is coupled to the capacitive network to receive the first and second bootstrapped signals on the first and second control inputs, respectively. The push-pull stage is operable to generate a buffered output signal on the output responsive to the first and second bootstrapped signals.

Abstract: A silicon chip surface mounted via balls attached to its front surface, wherein the front and rear surfaces of the chip are covered with a thermosetting epoxy resin having the following characteristics: the resin contains a proportion ranging from 45 to 60% by weight of a load formed of carbon fiber particles with a maximum size of 20 ?m and with its largest portion having a diameter ranging between 2 and 8 ?m, on the front surface side, the loaded resin covers from 45 to 60% of the ball height, on the rear surface side, the loaded resin has a thickness ranging between 80 and 150 ?m.

Abstract: A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor.

Abstract: A multi-processing system-on-chip including a cluster of processors having respective CPUs is operated by: defining a master CPU within the respective CPUs to coordinate operation of said multi-processing system, running on the CPU a cluster manager agent. The cluster manager agent is adapted to dynamically migrate software processes between the CPUs of said plurality and change power settings therein.

Abstract: A method for masking a digital quantity used by a calculation executed by an electronic circuit and including several iterations, each including at least one operation which is a function of at least one value depending on the digital quantity, the method including at least one first step of displacement of at least one operand of the operation in a storage element selected independently from the value.

Abstract: Data service transmission interruption is minimized by initially setting up a cluster of channels to transmit data services. As the need arises to switch channels due to the detection of an incumbent signal, the data services can be switched with substantially no delay. A group of channels from those available in a wireless network are chosen to form a cluster of channels. Each channel within the cluster is set up to convey data services with channel parameters being stored. A first operating channel is chosen from among the cluster of channels to transmit the data services. While the data services are being transmitted on the first operating channel, out-of-band spectrum sensing occurs on the other channels. Upon predetermined criteria a channel switch occurs. As each channel has already been set up the necessary channel parameters are retrieved from storage and restored without data service interruption.

Abstract: An electronic charge retention circuit for time measurement, implanted in an array of EEPROM memory cells, each including a selection transistor in series with a floating-gate transistor, the circuit including, on any one row of memory cells: a first subassembly of at least a first cell, the thickness of the dielectric of the tunnel window of the floating-gate transistor of which is less than that of the other cells; a second subassembly of at least a second cell, the drain and source of the floating-gate transistor of which are interconnected; a third subassembly of at least a third cell; and a fourth subassembly of at least a fourth cell, the tunnel window of which is omitted, the respective floating gates of the transistors of the cells of the four subassemblies being interconnected.

Abstract: A method for testing a memory device. The memory device includes a matrix of memory cells having a plurality of rows and columns; the matrix includes a plurality of rows of operative memory cells each one for storing a variable value and at least one row of auxiliary memory cells each one storing a fixed value. The memory device further includes writing circuitry for writing selected values into the operative memory cells, and reading circuitry for reading the values being stored from the operative or auxiliary memory cells. The method includes reading output values from the row of auxiliary memory cells, determining a malfunctioning of the memory device in response to a missing match of the output values with the fixed values, determining a cause of the malfunctioning according to a pattern of reading errors between the output values and the corresponding fixed values, and providing a signal indicative of the cause of the malfunctioning.