Abstract: An integrated circuit protected against electrostatic discharges, including: first and second supply rails; first and second intermediary rails normally connected to the first and second supply rails; inverters formed of a P-channel MOS transistor series-connected to an N-channel MOS transistor, the sources of the P-channel and N-channel MOS transistors being respectively connected to the first and second supply rails and the bodies of the P-channel and N-channel transistors being respectively connected to the first and second intermediary rails; a positive overvoltage detector between the first and second supply rails; and a switch for connecting the first and second intermediary rails to the second and first supply rails when a positive overvoltage is detected.

Abstract: A rasterizing method calculates an attribute (C) of a pixel having coordinates (X, Y) based on the coordinates (X0, Y0), (X1, Y1), (X2, Y2) of vertices of a primitive in a screen space, Z coordinates Z0, Z1 and Z2 of said vertices into the three-dimensional space, and attributes C0, C1, C2 of said vertices.

Abstract: The present disclosure provides a system and method for relieving stress and providing improved heat management in a 3D chip stack of a multichip package. A stress relief apparatus is provided to allow the chip stack to adjust in response to pressure, thereby relieving stress applied to the chip stack. Additionally, improved heat management is provided such that the chip stack adjusts in response to thermal energy generated within the chip stack to remove heat from between chips of the stack, thereby allowing the chips to operate as desired without compromising the performance of the chip stack. The chip stack also includes an array of flexible conductors disposed between two chips, thereby providing an electrical connection between the two chips.

Abstract: A method of successive approximation analog to digital conversion including: during a sample phase, coupling an input signal to a plurality of pairs of capacitors; and during a conversion phase, coupling a first capacitor of each pair to a first supply voltage, and a second capacitor of each pair to a second supply voltage.

Abstract: A capacitance-to-digital converter for an extended range of capacitances includes a reference capacitor and one or more offset capacitors. Electrical charge accumulated in the offset capacitors is used to at least partially cancel the charge accumulated in a sensed capacitance to facilitate matching with a charge accumulated in the reference capacitor. The residual charge is passed to an integrator, the output from which is quantized and used to control switching of the capacitors. Immunity to tonal external noises and improved conversion speed are achieved by controlling the capacitor switching with a spread spectrum clock. The capacitance-to-digital converter may be used, for example, for sensing of the capacitances of capacitive elements in touch and proximity displays or other user interfaces.

Abstract: The method for forming a multilayer structure on a substrate comprises providing a stack successively comprising an electron hole blocking layer, a first layer made from N-doped semiconductor material having a dopant concentration greater than or equal to 1018 atoms/cm3or P-doped semiconductor material, and a second layer made from semiconductor material of different nature. A lateral electric contact pad is made between the first layer and the substrate, and the material of the first layer is subjected to anodic treatment in an electrolyte.

Abstract: The present disclosure provides a system and method for detecting motion vectors in an image frame using a recursive hierarchical process with a non-rasterized vector-scanning motion to reduce erroneous motion vectors in an image frame of a digital video sequence. In general, a resolution hierarchy is generated for an image frame, wherein the resolution hierarchy comprises the original image frame and one or more copy image frames each having a different, lower resolution than the original image frame. Each image frame in the hierarchy is partitioned into image patches disposed in columns and rows, and the image patches are scanned in a non-rasterized motion to detect motion vectors in each image patch. The disclosed system and method provides faster convergence and improved accuracy by converging motion vectors in multiple directions and minimizing erroneous motion vectors in the image sequence.

Abstract: An embodiment of a simulation tool includes a path determiner and a simulator. The path determiner is configured to identify a first communication path between first and second devices of a system, and the simulator is configured to simulate a routing of a first item from one of the first and second devices to the other of the first and second devices via the identified path. The path determiner may also be configured to identify the communication path before the simulator simulates the routing of the item, or to identify the communication path while the simulator is inactive.

Abstract: A process is described for integrating two closely spaced thin films without deposition of the films through deep vias. The films may be integrated on a wafer and patterned to form a microscale heat-trimmable resistor. A thin-film heating element may be formed proximal to a thin-film resistive element, and heat generated by the thin-film heater can be used to permanently trim a resistance value of the thin-film resistive element. Deposition of the thin films over steep or abrupt topography is minimized by using a process in which the thin films are deposited in a sequence that falls between depositions of thick metal contacts to the thin films.

Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds.

Abstract: The present disclosure provides a system and method for relieving stress and providing improved heat management in a 3D chip stack of a multichip package. A stress relief apparatus is provided to allow the chip stack to adjust in response to pressure, thereby relieving stress applied to the chip stack. Additionally, improved heat management is provided such that the chip stack adjusts in response to thermal energy generated within the chip stack to remove heat from between chips of the stack, thereby allowing the chips to operate as desired without compromising the performance of the chip stack.

Abstract: A database stores updated information concerning protected communications services. A base station for a coexisting, and potentially co-channel, non-protected communications service makes an inquiry of the database requesting an identification of geographically relevant protected services along with the database stored information pertinent to each of those identified protected services. The returned information is processed by the base station to determine what channels are available for use by the non-protected service. An available channel is identified by the base station as the working channel for the non-protected service and the base station initiates a process to establish a communications network using the non-protected service and the selected working channel.

Abstract: An integrated circuit may include an element placed in an insulating region adjacent to a copper metallization level and including a barrier layer in contact with a metallization level. The element may be electrically connected to and spaced away from a copper line of the metallization level by way of an electrical link passing through the barrier layer and including an electrically conductive material different from copper in direct contact with the copper line.

Abstract: In an embodiment, a channel estimator includes first, second, and third stages. The first stage is configurable to generate a first observation scalar for a first communication path of a first communication channel, and the second stage is configurable to generate a second observation scalar for a first communication path of a second communication channel. And the third stage is configurable to generate channel-estimation coefficients in response to the first and second observation scalars. For example, such a channel estimator may use a recursive algorithm, such as a Vector State Scalar Observation (VSSO) Kalman algorithm, to estimate the responses of channels over which propagate simultaneous orthogonal-frequency-division-multiplexed (OFDM) signals (e.g., MIMO-OFDM signals) that suffer from inter-carrier interference (ICI) due to Doppler spread.

Abstract: In an embodiment, a channel estimator includes first and second stages. The first stage is configurable to generate an observation scalar for a communication path of a communication channel, and the second stage is configurable to generate channel-estimation coefficients in response to the first observation scalar. For example, such a channel estimator may use a recursive algorithm, such as a VSSO Kalman algorithm, to estimate the response of a channel over which propagates an OFDM signal that suffers from ICI due to Doppler spread. Such a channel estimator may estimate the channel response more accurately, more efficiently, with a less-complex algorithm, and with less-complex software or circuitry, than conventional channel estimators. Furthermore, such a channel estimator may be able to dynamically account for changes in the number of communication paths that compose the channel, changes in the delays of these paths, and changes in the signal-energy levels of these paths.

Abstract: A method of generating a reset signal for an integrated circuit without a dedicated reset pin includes calibrating a first clock pulse from a clock signal, measuring a second clock pulse from the clock signal, measuring a third clock pulse from the clock signal, and generating an internal reset signal if the first clock pulse width is longer than a predetermined minimum clock pulse width, if the second clock pulse is within an expected first value range, and if the third clock pulse is within an expected second value range.

Abstract: In an embodiment, a transmitter includes first and second transmission paths. The first transmission path is configurable to generate first pilot clusters each including a respective first pilot subsymbol in a first cluster position, and the second transmission path is configurable to generate second pilot clusters each including a respective second pilot subsymbol in a second cluster position such that a vector formed by the first pilot subsymbols is orthogonal to a vector formed by the second pilot subsymbols. For example, where such a transmitter transmits simultaneous orthogonal-frequency-division-multiplexed (OFDM) signals (e.g., MIMO-OFDM signals) over respective channels that may impart inter-carrier interference (ICI) to the signals due to Doppler spread, the pattern of the pilot symbols that compose the pilot clusters may allow a receiver of these signals to use a recursive algorithm, such as a Vector State Scalar Observation (VSSO) Kalman algorithm, to estimate the responses of these channels.

Abstract: A method and system for managing the power supply of a component and of a memory cooperating with the component are disclosed. The component and the memory are powered with a first variable power supply source having a first power supply voltage level greater than a minimum operating voltage of the memory. When a voltage level of the first power supply source drops and reaches a threshold that is greater than or equal to the minimum operating voltage of the memory, the power supply of the memory is toggled to a second power supply source having a second voltage level that is greater than or equal to the minimum operating voltage of the memory.

Abstract: An integrated circuit includes a substrate of semiconductive material, a first circuit environment made from the substrate which includes an output terminal and a first pair of power supply terminals for receiving a first power supply voltage applicable between the terminals. The integrated circuit also includes a second circuit environment made from the semiconductor substrate which includes an input terminal electrically coupled to the output terminal and also includes a second pair of power supply terminals for receiving a second power supply voltage applicable between the second pair of terminals of said second pair. The circuit further includes a device providing protection from electrostatic discharges which includes an integrated resistive device coupled between the input and output terminals.

Abstract: Method for manufacturing a semiconductor pressure sensor, wherein, in a silicon substrate, trenches are dug and delimit walls; a closing layer is epitaxially grown, that closes the trenches at the top and forms a suspended membrane; a heat treatment is performed so as to cause migration of the silicon of the walls and to form a closed cavity underneath the suspended membrane; and structures are formed for transducing the deflection of the suspended membrane into electrical signals.