Abstract: A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.
Abstract: A micro device includes a substrate and a structure configured to bind to an object or a material, or not to bind to an object or material. The structure has a roughness based on a roughness of the object or material. For example, a microarray includes a substrate and a well positioned in the substrate and configured to bind to a type of bead. The well has a roughness based on a roughness of the type of bead to which the well is configured to bind. The roughness of the well is controlled by controlling a position and number of striations in the side of the well. In another example, a moveable component of a micro device may have a roughness different from a roughness of an adjacent component, to reduce the likelihood of the moveable component sticking to the adjacent component.
Type:
Application
Filed:
October 12, 2011
Publication date:
April 19, 2012
Applicant:
STMICROELECTRONICS, INC.
Inventors:
Massimiliano Pesaturo, Robert J. Powell
Abstract: A system for edge enhancement includes an input unit to receive an input signal Yin, a vertical enhancement unit to perform a vertical enhancement of an edge of the input signal Yin to generate an output YEV, and a horizontal enhancement unit to perform a horizontal enhancement of the edge of the input signal Yin to generate an output YEH. The system also includes a local gradient analysis unit to generate a local gradient direction GradDir and a local gradient magnitude GradMag based at least partly upon the input signal Yin, and a mixer to generate an output Yout by mixing the output YEV with the output YEH using the local gradient direction GradDir. The system further includes an output unit to output the output Yout.
Type:
Application
Filed:
October 15, 2010
Publication date:
April 19, 2012
Applicants:
STMicroelectronics (Grenoble 2) SAS, STMicroelectronics Asia Pacific Pte. Ltd.
Abstract: The disclosure relates to a method for reconstruction of a three-dimensional image of an object. A first image is acquired of the object lit by a luminous flux having, in a region including the object, a luminous intensity dependant on the distance, with a light source emitting the luminous flux. A second image is acquired of the object lit by a luminous flux having, in a region including the object, a constant luminous intensity. For each pixel of a three-dimensional image, a relative distance of a point of the object is determined as a function of the intensity of a pixel corresponding to the point of the object in each of the acquired images.
Abstract: A method and a device for converting a first bus including at least a data wire and a clock wire into a single-wire bus, wherein a data bit of the first bus is converted on half a period of the clock signal for transmission over the second bus, a waiting pattern being placed on the second bus during the other half-period.
Type:
Grant
Filed:
July 14, 2009
Date of Patent:
April 17, 2012
Assignees:
STMicroelectronics (Rousset) SAS, Proton World Internationl N.V.
Abstract: Silicon-based single-crystal portions are produced on a surface of a substrate, selectively in zones where a single-crystal material is initially exposed. To do this, a layer is firstly formed over the entire surface of the substrate, using a silicon precursor of the non-chlorinated hydride type, and under suitable conditions so that the layer is a single-crystal layer in the zones of the substrate where a single-crystal material is initially exposed and amorphous outside these zones. The amorphous portions of the layer are then selectively etched so that only the single-crystal portions of the layer remain on the substrate.
Abstract: A microresonator comprising a single-crystal silicon resonant element and at least one activation electrode placed close to the resonant element, in which the resonant element is placed in an opening of a semiconductor layer covering a substrate, the activation electrode being formed in the semiconductor layer and being level at the opening.
Abstract: A method is for making an integrated circuit with built-in self-test. The method includes forming at least one nonvolatile read only memory (ROM) to store ROM code and forming a logic self-test circuit to verify a correct functioning of the at least one nonvolatile ROM. Moreover, the method includes defining, in the logic self-test circuit, a logic self-test core to process the ROM code and to generate a flag based upon a control signature and defining, in the logic self-test circuit, a nonvolatile storage block, coupled to the logic self-test core, to store the control signature. Furthermore, the method includes writing the ROM code to the at least one nonvolatile ROM and writing the control signature to the nonvolatile storage block, during a same fabrication step.
Abstract: The present disclosure relates to an integrated circuit and a package on which such integrated circuit is placed, the latter having a power output stage, at least one first pad, one second pad and one drive circuit for driving said power output stage, wherein the integrated circuit is characterized in that it has at least one additional third pad, other than said at least one first and said at least one second pads, said drive circuit being electrically coupled between said at least one third pad and said power output stage.
Abstract: A method of reading voltages from an image sensor having an array of pixels, each pixel Having at least one photodiode connectable to a storage node, the method including: controlling each pixel in a row of pixels to store and output a first voltage value at a first instance, a second voltage value at a second instance, and a third voltage value at a third instance, the first, second and third voltage values being representative of charge accumulated by the photodiodes during an integration phase; comparing the first voltage value from each pixel with a reference threshold; sampling for each pixel, based on the comparison, one of the second and third voltage values, and generating an output pixel value based on the sampled one of the second and third voltage values.
Abstract: A process for manufacturing a MOS device includes forming a semiconductor layer having a first type of conductivity; forming an insulated gate structure having an electrode region (25), above the semiconductor layer (23); forming body regions having a second type of conductivity, within the semiconductor layer, laterally and partially underneath the insulated gate structure; forming source regions having the first type of conductivity, within the body regions; and forming a first enrichment region, in a surface portion of the semiconductor layer underneath the insulated gate structure. The first enrichment region has the first type of conductivity and is set at a distance from the body regions. In order to form the first enrichment region, a first enrichment window is defined within the insulated gate structure, and first dopant species of the first type of conductivity are introduced through the first enrichment window and in a way self-aligned thereto.
Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b?1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.
Abstract: An image stabilization apparatus includes accelerometers, a proximity sensor and a processor. Each accelerometer determines acceleration along an axis of a plane parallel to a focal plane of an image capture device. The accelerometers output respective acceleration data to the processor. The proximity sensor obtains a measurement of the distance between the focal plane of the image capture device and an object plane. The proximity sensor outputs distance data to the processor. The processor processes the distance data and the acceleration data to produce correction data to correct image data captured during motion of the image capture device.
Abstract: An apparatus for measuring time interval between two selected edges of a clock signal. includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first constant incremental delay at each tap to the first edge. Second multi-tap delay module provides a second constant incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has a first input terminal and a second input terminal. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.
Abstract: A method and a circuit for protecting the execution of a program, including initializing at least one counter, carrying on with the normal program execution, interrupting this execution when the counter reaches a given value, and executing at least one integrity check of the calculation after this interrupt.
Abstract: An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether, for each bundle, multiple instances can be executed in parallel. If multiple instances can be executed in parallel, coupling circuitry couples an instance of the bundle from one lane into one or more other lanes. In each lane, register addresses are renamed to ensure proper execution of the bundles in the vector run. Additionally, the processor may include a register bank separate from the architectural register file. Renaming logic can generate addresses to this separate register bank that are longer than used to address architectural registers, allowing longer vectors and more efficient processor operation.
Abstract: An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.
Type:
Application
Filed:
October 11, 2010
Publication date:
April 12, 2012
Applicants:
STMICROELECTRONICS ASIA PACIFIC PTE. LTD., STMICROELECTRONICS, INC.
Inventors:
Olivier Le Neel, Fuchao Wang, Ravi Shankar
Abstract: An electroacoustic transducer including a first electrode formed on a substrate capable of transmitting ultrasounds, a membrane formed above the first electrode and separated therefrom by a cavity, a second electrode formed on the membrane, a first insulating layer on the second electrode, and a third electrode formed on the first insulating layer.
Abstract: A modular device having at least one master integrated circuit, and one or more slave integrated circuit modules coupled to the at least one master integrated circuit with each slave integrated circuit module of the one or more slave integrated circuit modules coupled to and associated with only a single cell of the battery. Each slave integrated circuit module of the one or more slave integrated circuit modules further comprises: detection circuitry adapted to detect data comprising one or more of the temperature, voltage or charge status, and malfunctioning of the single cell associated with and monitored by the slave integrated circuit; and an interface operable to send said detected data to the at least one master integrated circuit. The at least one master integrated circuit is adapted to send commands to a slave integrated circuit module in response to the detected data detected by the slave integrated circuit module.
Abstract: A backside image sensor including an assembly of pixels, each pixel including, in a vertical stack, a photosensitive area and a filtering element topping the photosensitive area on the back surface side, wherein at least two adjacent filtering elements of adjacent pixels are separated by a vertical metal wall extending over at least eighty percent of the height of the filtering elements or over a greater height.