Abstract: The electronic control unit includes a communication circuit adapted to receive intelligent transport system messages, an authentication circuit designed to authenticate the received messages, a non-volatile memory configured to record the authenticated received messages, and a secure element. The secure element includes a blacklist of automatically excluded senders and is configured to directly reject a received message from a sender on the blacklist without authentication using the authentication circuit. Alternatively, the secure element includes a whitelist of automatically allowed senders and is configured to directly record a received message from a sender on the whitelist in the non-volatile memory without authentication using the authentication circuit.

Abstract: An irrigation system includes a first valve fluidly-coupled between an inlet pipe and an outlet pipe, and a second valve fluidly-coupled between the inlet pipe and a power harvester. The power harvester generates electrical power at a power output in response to fluid flowing therethrough. An energy storage unit is coupled to the power output to store generated voltage. Comparison circuitry compares the generated voltage to a threshold. Control circuitry causes the second valve to permit fluid to flow therethrough when the generated voltage is less than the threshold, causing generation of the electrical power by the power harvester when the generated voltage is less than the threshold. The comparison circuitry causes the second valve to prevent fluid flow when the generated voltage is at least equal to threshold, ceasing generation of the electrical power by the power harvester when the generated voltage is at least equal to the threshold.

Abstract: A System in Package, SiP semiconductor device includes a substrate of laser direct structuring, LDS, material. First and second semiconductor die are arranged at a first and a second leadframe structure at opposite surfaces of the substrate of LDS material. Package LDS material is molded onto the second surface of the substrate of LDS material. The first semiconductor die and the package LDS material lie on opposite sides of the substrate of LDS material. A set of electrical contact formations are at a surface of the package molding material opposite the substrate of LDS material. The leadframe structures include laser beam processed LDS material. The substrate of LDS material and the package LDS material include laser beam processed LDS material forming at least one electrically-conductive via providing at least a portion of an electrically-conductive line between the first semiconductor die and an electrical contact formation at the surface of the package molding material opposite the substrate.

Abstract: A three-phase load is powered by an SPWM driven inverter having a single shunt-topology. During operation, drain-to-source resistances of transistors of each branch of the inverter are determined. Interpolation is performed on assumed drain-to-source resistances of the transistors for different temperatures to produce a non-linear model of drain-to-source resistance to temperature for the transistors, and the drain-to-source resistances determined during operation and the non-linear model are used to estimate temperature values of the transistors. Driving of the inverter can be adjusted so that conductivity of each branch is set so that power delivered by that branch is as high as possible without exceeding an allowed drain current threshold representing a threshold junction temperature. In addition, driving of the inverter can be ceased if the temperature of a transistor exceeds the threshold temperature.

Abstract: The latch device includes an RS type latch flip-flop capable of being supplied between a first supply voltage and a second supply voltage which is lower than the first supply voltage and having first and second flip-flop inputs and a flip-flop output connected to the output terminal. A control module positions the latch flip-flop in a set state or in a reset state when the first supply voltage has a first value which is lower than the low voltage then, the latch flip-flop being positioned, confers the high voltage on the first supply voltage and the low voltage on the second supply voltage and outputs and maintains the high voltage or the low voltage on the flip-flop output while avoiding outputting a prohibited logic state at the two flip-flop inputs.

Abstract: A thin-film lithium ion battery includes a negative electrode layer, a positive electrode layer, an electrolyte layer disposed between the positive and negative electrode layers, and a lithium layer with lithium pillars extending therefrom formed in the negative electrode layer adjoining the electrolyte layer.

Abstract: Disclosed herein is an electronic control unit including a communication circuit designed to receive intelligent transport system (ITS) messages, an authentication circuit for authenticating the received messages, and a secure element containing a hardware-secure non-volatile memory and a continually active clock counter.

Abstract: An integrated-circuit package includes a flexible electrical-connection element sandwiched between a first face of a first multilayer support substrate and a second face of a second multilayer support substrate. The flexible electrical-connection element laterally projects with respect to, and is in electrical contact with at least one of, the multilayer support substrates. The flexible electrical-connection element and the first multilayer support substrate include, at a first region, respectively two first mutually facing orifices defining together a first cavity. The first cavity is at least partially closed off by a first part of the second face of the second multilayer support substrate. A first component is located in the first cavity, attached at the first part of the second face of the second multilayer support substrate and in electrical contact with the flexible electrical-connection element through the second multilayer support substrate.

Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.

Abstract: Disclosed herein is a control system for a projection system, including a first subtractor receiving an input drive signal and a feedback signal and generating a first difference signal therefrom, the feedback signal being indicative of position of a quasi static micromirror of the projection system. A type-2 compensator receives the first difference signal and generates therefrom a first output signal. A derivative based controller receives the feedback signal and generates therefrom a second output signal. A second subtractor receives the first and second output signals and generates a second difference signal therefrom. The second difference signal serves to control a mirror driver of the projection system. A higher order resonance equalization circuit receives a pre-output signal from an analog front end of the projection system that is indicative of position of the quasi static micromirror, and generates the feedback signal therefrom.

Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.

Abstract: A driving circuit for a microelectromechanical system (MEMS) gyroscope operating based on the Coriolis effect is provided. The driving circuit supplies drive signals to a mobile mass of the MEMS gyroscope to cause a driving movement of the mobile mass to oscillate at an oscillation frequency. The driving circuit includes an input stage, which receives at least one electrical quantity representing the driving movement and generates a drive signal based on the electrical quantity; a measurement stage, which measures an oscillation amplitude of the driving movement based on the drive signal; and a control stage, which generates the drive signals based on a feedback control of the oscillation amplitude. The measurement stage performs a measurement of a time interval during which the drive signal has a given relationship with an amplitude threshold, and measures the oscillation amplitude as a function of the time interval.

Abstract: An integrated device includes at least one MOS transistor having a plurality of cells. In each of one or more of the cells a disabling structure is provided. The disabling structure is configured to be in a non-conductive condition when the MOS transistor is switched on in response to a control voltage comprised between a threshold voltage of the MOS transistor and an intervention voltage of the disabling structure, or to be in a conductive condition otherwise. A system comprising at least one integrated device as above is also proposed. Moreover, a corresponding process for manufacturing this integrated device is proposed.

Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.

Abstract: A method for operating an electronic device includes detecting, by a touchscreen controller, a touch point on a touchscreen; determining, by the touchscreen controller, coordinates of the touch point; scaling, by the touchscreen controller, up the coordinates of the touch point to obtain scaled up coordinates by overwriting a reserved portion of a touch event protocol with additional information corresponding to the coordinates of the touch point; reporting, by the touchscreen controller, the scaled up coordinates of the touch point to an application processor; and determining, by the application processor, the coordinates of the touch point with an increased resolution by converting the scaled up coordinates into a floating point value.

Abstract: An indirect time-of-flight measurement sensor includes a photosensitive pixel array configured to acquire a succession of images of a scene during a given exposure time. The sensor includes a control unit configured to control the acquisition of the succession of images by the pixel array and to define an exposure time for this acquisition based on a pixel saturation rate of the array, distances between the sensor and elements of the scene, and a standard deviation of the distances between the sensor and the elements of the scene.

Abstract: A first circuit is coupled to a second circuit via a communication link. The first circuit generates a first validation signal, a second validation signal, and control signals, and transmits the first and second validation signals to the second circuit via the communication link. The second circuit validates the control signals based on the first and second binary validation signals. The validating includes: verifying that when the first validation signal has a first value, the second validation signal has a second value different from the first value; verifying that when the second validation signal has the first value, the first validation signal has the second value; verifying detection of a transition edge of the first validation signal within a threshold number of clock cycles; and verifying detection of a transition edge of the second validation signal within the threshold number of clock cycles.

Abstract: A PFC correction circuit includes first, second, and third phase inputs coupled to three-phase power mains, with a three-phase full-wave rectifying bridge connected to an input node. First, second, and third boost inductors are respectively connected between first, second, and third phase inputs and first, second, and third taps of the three-phase full-wave rectifying bridge. A boost switch is connected between the input node and ground, and a boost diode is connected between the input node and an output node. A multiplier input driver generates a single-phase input signal as a replica of a signal at the three-phase power mains after rectification. A single-phase power factor controller generates a PWM signal from the single-phase input signal. A gate driver generates a gate drive signal from the PWM signal. The boost switch is operated by the gate drive signal.

Abstract: A sensor includes detection circuitry and control circuitry coupled to the detection circuitry. The detection circuitry generates a detection signal indicative of a detected physical quantity. The control circuitry, in operation receives the detection signal and a frequency-indication signal, and generates a trigger signal based on the frequency-indication signal and a set of local reference signals. The sensor generates a digital output signal and a locking signal based on the trigger signal and the detection signal. The generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal. The locking signal is temporally aligned with the digital output signal.

Abstract: Techniques and systems are provided for implementing a convolutional neural network. One or more convolution accelerators are provided that each include a feature line buffer memory, a kernel buffer memory, and a plurality of multiply-accumulate (MAC) circuits arranged to multiply and accumulate data. In a first operational mode the convolutional accelerator stores feature data in the feature line buffer memory and stores kernel data in the kernel data buffer memory. In a second mode of operation, the convolutional accelerator stores kernel decompression tables in the feature line buffer memory.