Patents Assigned to Sumco Techxiv Corporation
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Patent number: 8992791Abstract: A silicon wafer surface other than a defect is oxidized by ozone to form a silicon oxide film. A hydrofluoric acid is sprayed and subsequently a cleaning gas is sprayed onto the surface of the silicon wafer.Type: GrantFiled: September 30, 2009Date of Patent: March 31, 2015Assignee: Sumco Techxiv CorporationInventors: Kazuaki Kozasa, Tomonori Kawasaki, Takahisa Sugiman, Hironori Nishimura
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Patent number: 8961686Abstract: For manufacturing a monocrystal, a monocrystal pulling-up device controls pressure within a flow straightening cylinder to be from 33331 Pa to 79993 Pa and a flow velocity of inert gas in the cylinder to be from 0.06 m/sec to 0.31 m/sec (0.005 to 0.056 SL/min·cm2) during a post-addition-pre-growth period. By controlling the flow velocity of the inert gas to be in the above-described range during the post-addition-pre-growth period, the inert gas flows smoothly even when the pressure within the cylinder is relatively high. Evaporation of a volatile dopant because of a reverse flow of the inert gas can be restrained. The volatile dopant can be prevented from adhering to the flow straightening cylinder in an amorphous state, and the volatile dopant can be prevented from dropping into a melt or sticking on the melt while growing a crystal. Foulings can be easily removed.Type: GrantFiled: July 25, 2008Date of Patent: February 24, 2015Assignee: Sumco Techxiv CorporationInventors: Shinichi Kawazoe, Fukuo Ogawa, Yasuhito Narushima, Toshimichi Kubota
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Patent number: 8956927Abstract: A method of manufacturing an epitaxial silicon wafer including a silicon wafer having a surface added with phosphorus and an epitaxial film provided on the surface includes adjusting an in-plane thickness distribution of the epitaxial film formed on the surface of the silicon wafer based on an in-plane resistivity distribution of the silicon wafer before an epitaxial growth treatment.Type: GrantFiled: June 13, 2013Date of Patent: February 17, 2015Assignee: Sumco Techxiv CorporationInventors: Tadashi Kawashima, Naoya Nonaka
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Patent number: 8920561Abstract: A silicon single crystal pull-up apparatus includes a pull-up furnace, a sample chamber in which a sublimable dopant is housed, a sample tube which can be raised and lowered between the interior of the sample chamber and the interior of the pull-up furnace, a raising and lowering means for raising and lowering the sample tube, a supply pipe which is installed inside the pull-up furnace and supplies the sublimable dopant to a melt, and a connection means for connecting the sample tube and the supply pipe. The connection means is constructed from a ball joint structure comprising a convex member which projects from one end of the sample tube and a concave member which is provided at one end of the supply pipe and is formed to be engageable with the convex member. The contact surfaces of the convex member and the concave member are formed to be curved surfaces.Type: GrantFiled: July 28, 2009Date of Patent: December 30, 2014Assignee: Sumco Techxiv CorporationInventors: Yasuhito Narushima, Shinichi Kawazoe, Fukuo Ogawa, Toshimichi Kubota, Tomohiro Fukuda
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Patent number: 8906777Abstract: A method for evaluating a shape change of a semiconductor wafer is provided. The method comprises acquiring unconstrained shape data of shape data of the semiconductor wafer being placed on a reference surface in a unconstrained state; acquiring constrained shape data of shape data of the semiconductor wafer being constrained along the reference surface in a constrained state; and comparing the unconstrained shape data and the constrained shape data. A method for manufacturing the semiconductor wafer utilizing a result of the evaluation of the wafer is also provided.Type: GrantFiled: January 29, 2009Date of Patent: December 9, 2014Assignee: Sumco Techxiv CorporationInventors: Kazuhiro Iriguchi, Toshiyuki Isami, Kouhei Kawano
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Patent number: 8888911Abstract: The present invention provides a technique which enables production of single crystal silicon having relatively low resistivity by preventing cell growth during crystal growth from occurring, especially in a case where a relatively large amount of dopant is added to a molten silicon raw material. Specifically, the present invention provides a method of producing single crystal silicon by the Czochralski process, comprising producing single crystal silicon having relatively low resistivity by controlling a height of a solid-liquid interface when the single crystal silicon is pulled up.Type: GrantFiled: September 3, 2010Date of Patent: November 18, 2014Assignee: Sumco Techxiv CorporationInventors: Masayuki Uto, Tuneaki Tomonaga, Toshimichi Kubota, Fukuo Ogawa, Yasuhito Narushima
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Patent number: 8888913Abstract: A method of forming an epitaxial layer to increase flatness of an epitaxial silicon wafer is provided. In particular, a method of controlling the epitaxial layer thickness in a peripheral part of the wafer is provided. An apparatus for manufacturing an epitaxial wafer by growing an epitaxial layer with reaction of a semiconductor wafer and a source gas in a reaction furnace comprising: a pocket in which the semiconductor wafer is placed; a susceptor fixing the semiconductor; orientation-dependent control means dependent on a crystal orientation of the semiconductor wafer and/or orientation-independent control means independent from the crystal orientation of the semiconductor wafer, wherein the apparatus may improve flatness in a peripheral part of the epitaxial layer.Type: GrantFiled: August 9, 2011Date of Patent: November 18, 2014Assignee: Sumco Techxiv CorporationInventors: Kazuhiro Narahara, Hirotaka Kato, Koichiro Hayashida
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Patent number: 8852340Abstract: In consideration of influence of segregation, an evaporation area of a volatile dopant and influence of pulling-up speed at the time of manufacturing a monocrystal using a monocrystal pulling-up device, an evaporation speed formula for calculating evaporation speed of the dopant is derived. At predetermined timing during pulling-up, gas flow volume and inner pressure in a chamber are controlled such that a cumulative evaporation amount of the dopant, calculated based on the evaporation speed formula, becomes a predetermined amount. A difference between a resistivity profile of the monocrystal predicted based on the evaporation speed formula and an actual resistivity profile is made small. Since no volatile dopant is subsequently added, increase in workload on an operator, increase of manufacturing time, an increase in amorphous adhering to the inside of the chamber, and an increase in workload at the time of cleaning the inside of the chamber can be prevented.Type: GrantFiled: October 4, 2013Date of Patent: October 7, 2014Assignee: Sumco Techxiv CorporationInventors: Yasuhito Narushima, Fukuo Ogawa, Shinichi Kawazoe, Toshimichi Kubota
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Patent number: 8853103Abstract: A method of manufacturing a silicon wafer, an oxygen concentration in a surface layer to be maintained more than a predetermined value while promoting a defect-free layer. Strength of the surface layer can be made higher than that of an ordinary annealed sample as a COP free zone is secured. A method of manufacturing a silicon wafer doped with nitrogen and oxygen, includes growing a single crystal silicon doped with the nitrogen by Czochralski method, slicing the grown single crystal silicon to obtain a single crystal silicon wafer; heat treating the sliced single crystal silicon wafer in an ambient gas including a hydrogen gas and/or an inert gas; polishing the heat treated single crystal silicon wafer, after the heat treatment, such that an obtained surface layer from which COP defects have been removed by the heat treatment is polished away until an outermost surface has a predetermined oxygen concentration.Type: GrantFiled: March 15, 2013Date of Patent: October 7, 2014Assignee: Sumco Techxiv CorporationInventor: Shinya Sadohara
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Patent number: 8840721Abstract: The present invention provides a method of producing low-resistivity silicon single crystal containing a dopant at a relatively high concentration by adding a large amount of the dopant to silicon melt when the silicon single crystal is pulled up, with suppressing occurrence of dislocation in the crystal. Specifically, the present invention provides a method of manufacturing silicon single crystal by bringing silicon seed crystal into contact with silicon melt and pulling up the silicon seed crystal while rotating the crystal to grow silicon single crystal whose straight body section has a diameter of ? mm below the silicon seed crystal, the method comprising: the dopant-adding step of adding a dopant to the silicon melt during growth of the straight body section of the silicon single crystal, while rotating the silicon single crystal at a rotational speed of ? rpm (where ??24?(?/25)).Type: GrantFiled: November 11, 2010Date of Patent: September 23, 2014Assignee: Sumco Techxiv CorporationInventors: Yasuhito Narushima, Fukuo Ogawa, Toshimichi Kubota
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Patent number: 8747551Abstract: After adding phosphorus (P) and germanium (Ge) into a silicon melt or adding phosphorus into a silicon/germanium melt, a silicon monocrystal is grown from the silicon melt by a Czochralski method, where a phosphorus concentration [P]L(atoms/cm3) in the silicon melt, a Ge concentration in the silicon monocrystal, an average temperature gradient Gave (K/mm) and a pull speed V (mm/min) are controlled to satisfy a formula (1) as follows, a phosphorus concentration [P](atoms/cm3) and the Ge concentration [Ge](atoms/cm3) in the silicon monocrystal satisfy a relationship according to a formula (2) as follows while growing the silicon monocrystal, where dSi(?) represents a lattice constant of silicon, rSi(?) represents a covalent radius of silicon, rP(?) represents a covalent radius of phosphorus, and rGe(?) represents a covalent radius of Ge: [ P ] L + ( 0.3151 × [ Ge ] + 3.806 × 10 18 ) / 1.5 < 0.Type: GrantFiled: September 26, 2013Date of Patent: June 10, 2014Assignee: Sumco Techxiv CorporationInventors: Shinichi Kawazoe, Yasuhito Narushima, Toshimichi Kubota, Fukuo Ogawa
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Patent number: 8715416Abstract: A doping device includes a first dopant accommodating portion including an opening on an upper portion to accommodate a first dopant that is evaporated near a surface of a semiconductor melt; a second dopant accommodating portion including a dopant holder that holds a second dopant that is liquefied near the surface of the semiconductor melt while including a communicating hole for delivering the liquefied dopant downwardly, and a conduit tube provided on a lower portion of the dopant holder for delivering the liquefied dopant flowed from the communicating hole to the surface of the semiconductor melt; and a guide provided by a cylinder body of which a lower end is opened and an upper end is closed for guiding dopant gas generated by evaporation of the first dopant to the surface of the semiconductor melt.Type: GrantFiled: May 23, 2008Date of Patent: May 6, 2014Assignee: Sumco Techxiv CorporationInventors: Yasuhito Narushima, Shinichi Kawazoe, Fukuo Ogawa, Toshimichi Kubota
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Patent number: 8696809Abstract: A manufacturing method of an epitaxial silicon wafer is provided. The epitaxial silicon wafer includes: a substrate cut out from a silicon monocrystal that has been manufactured, doped with nitrogen and pulled up in accordance with Czochralski method; and an epitaxial layer formed on the substrate. The manufacturing method includes: cleaning a surface of the substrate with fluorinated acid by spraying onto the surface of the substrate fluorinated acid vaporized by a bubbling tank of a substrate cleaning apparatus; and forming an epitaxial layer on the cleaned surface of the substrate.Type: GrantFiled: June 12, 2008Date of Patent: April 15, 2014Assignee: Sumco Techxiv CorporationInventors: Kazuaki Kozasa, Kosuke Miyoshi
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Patent number: 8662961Abstract: A seasoning plate is placed on a polishing pad and performs seasoning of the polishing pad by abrading the polishing pad through the friction caused by rotation of the polishing pad. The seasoning plate includes: conditioners that abrade the polishing pad; a round flexible substrate that has the conditioners attached to the lower face thereof; an O-ring that is placed on the upper face of the flexible substrate, the O-ring forming a circle concentric with the flexible substrate; and a weight plate serving as a weight portion that is placed on the O-ring and applies weight for deforming the flexible substrate.Type: GrantFiled: October 28, 2009Date of Patent: March 4, 2014Assignee: Sumco Techxiv CorporationInventors: Daisuke Maruoka, Koudai Moroiwa
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Patent number: 8580032Abstract: In consideration of influence of segregation, an evaporation area of a volatile dopant and influence of a pulling-up speed at the time of manufacturing a monocrystal by use of a monocrystal pulling-up device, an evaporation speed formula for calculating an evaporation speed of the dopant is derived. At a predetermined timing during pulling-up, gas flow volume and inner pressure in a chamber are controlled such that a cumulative evaporation amount of the dopant, calculated based on the evaporation speed formula, becomes a predetermined amount. A difference between a resistivity profile of the monocrystal predicted based on the evaporation speed formula and an actual resistivity profile is made small. Since no volatile dopant is subsequently added, increase in workload on an operator, increase of manufacturing time, an increase in amorphous adhering to the inside of the chamber, and an increase in workload at the time of cleaning the inside of the chamber can be prevented.Type: GrantFiled: May 7, 2008Date of Patent: November 12, 2013Assignee: Sumco Techxiv CorporationInventors: Yasuhito Narushima, Fukuo Ogawa, Shinichi Kawazoe, Toshimichi Kubota
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Patent number: 8573969Abstract: A silicon wafer preferable to a semiconductor device is produced by determining a heat treatment condition hardly causing slip dislocations and heat-treating the silicon wafer under the condition. The resistance is calculated by using a calculation formula used for predicting the slip resistance of the wafer from the density, size, and residual solid-solution oxygen concentration of the oxygen precipitation in the silicon wafer, the state of oxygen precipitation such that heat treatment not causing any slip dislocation can be carried out is designed, and thus a silicon wafer heat treatment method under the heat treatment condition not causing any slip dislocation is determined. A silicon wafer heat-treated under such a condition can be provided.Type: GrantFiled: September 28, 2007Date of Patent: November 5, 2013Assignee: Sumco TechXIV CorporationInventors: Shinya Sadohara, Kozo Nakamura, Shiro Yoshino
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Patent number: 8574363Abstract: After adding phosphorus (P) and germanium (Ge) into a silicon melt or adding phosphorus into a silicon/germanium melt, a silicon monocrystal is grown from the silicon melt by a Czochralski method, where a phosphorus concentration [P]L (atoms/cm3) in the silicon melt, a Ge concentration in the silicon monocrystal, an average temperature gradient Gave (K/mm) and a pull speed V (mm/min) are controlled to satisfy a formula (1) as follows, the phosphorus concentration [P] (atoms/cm3) in the silicon monocrystal is 4.84×1019 atoms/cm3 or more and 8.49×1019 atoms/cm3 or less, and the phosphorus concentration [P] (atoms/cm3) and the Ge concentration [Ge] (atoms/cm3) in the silicon monocrystal satisfy a relationship according to a formula (2) as follows while growing the silicon monocrystal. [P]L+(0.3151×[Ge]+3.806×1019)/1.5<0.5×(Gave/V+43)×1019??(1) [Ge]?6.95×[P]+5.90×1020??(2).Type: GrantFiled: May 23, 2008Date of Patent: November 5, 2013Assignee: Sumco Techxiv CorporationInventors: Shinichi Kawazoe, Yasuhito Narushima, Toshimichi Kubota, Fukuo Ogawa
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Patent number: 8545712Abstract: In a method of manufacturing semiconductor wafers, front and back surfaces of the semiconductor wafers are simultaneously polished with a double-side polishing machine that includes: a carrier for accommodating the semiconductor wafer; and an upper press platen and a lower press platen for sandwiching the carrier. The method includes: accommodating the semiconductor wafer in the carrier while a thickness of the semiconductor wafer is set to be larger than a thickness of the carrier by 0 ?m to 5 ?m; and polishing the semiconductor wafer while feeding a polishing slurry to between the surfaces of the semiconductor wafer and surfaces of the press platens. In the polishing, an allowance of both surfaces of the semiconductor wafer is set at 5 ?m or less in total.Type: GrantFiled: September 11, 2008Date of Patent: October 1, 2013Assignee: Sumco Techxiv CorporationInventors: Hiroshi Takai, Kenji Satomura, Yuichi Nakayoshi, Katsutoshi Yamamoto, Kouji Mizowaki
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Patent number: 8535439Abstract: To provide a manufacturing method for a silicon single crystal that can reduce introduction of dislocation thereinto even if a required amount of dopant is added to a melt while growing a straight body portion of a silicon ingot. In a manufacturing method for a silicon single crystal according to the present invention that includes a dopant addition step of adding a dopant to a melt while a straight body portion of a silicon single crystal is growing in a growth step of growing the silicon single crystal by dipping a seed crystal into a silicon melt and then pulling the seed crystal therefrom, in the dopant addition step, a remaining mass of the melt is calculated at the beginning thereof, and the dopant is added to the melt at a rate of 0.01 to 0.035 g/min·kg per minute per 1 kg of the calculated remaining mass of the melt.Type: GrantFiled: January 8, 2010Date of Patent: September 17, 2013Assignee: Sumco Techxiv CorporationInventors: Yasuhito Narushima, Toshimichi Kubota, Shinichi Kawazoe, Fukuo Ogawa, Tomohiro Fukuda
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Patent number: 8518180Abstract: A silicon single crystal pull-up apparatus is used to pull up a doped silicon single crystal from a melt by means of the Czochralski process and includes a pull-up furnace, a sample chamber which is externally mounted on the pull-up furnace and houses a sublimable dopant, a shielding means for thermally isolating the interior of the pull-up furnace and the interior of the sample chamber, a sample tube which can be raised and lowered between the interior of the sample chamber and the interior of the pull-up furnace, and a raising and lowering means which is provided with guide rails on which the sample tube can slide and a wire mechanism by which the sample tube is raised and lowered along the guide rails.Type: GrantFiled: July 28, 2009Date of Patent: August 27, 2013Assignee: Sumco Techxiv CorporationInventors: Yasuhito Narushima, Shinichi Kawazoe, Fukuo Ogawa, Toshimichi Kubota, Tomohiro Fukuda