Patents Assigned to Sumco Techxiv Corporation
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Patent number: 8580032Abstract: In consideration of influence of segregation, an evaporation area of a volatile dopant and influence of a pulling-up speed at the time of manufacturing a monocrystal by use of a monocrystal pulling-up device, an evaporation speed formula for calculating an evaporation speed of the dopant is derived. At a predetermined timing during pulling-up, gas flow volume and inner pressure in a chamber are controlled such that a cumulative evaporation amount of the dopant, calculated based on the evaporation speed formula, becomes a predetermined amount. A difference between a resistivity profile of the monocrystal predicted based on the evaporation speed formula and an actual resistivity profile is made small. Since no volatile dopant is subsequently added, increase in workload on an operator, increase of manufacturing time, an increase in amorphous adhering to the inside of the chamber, and an increase in workload at the time of cleaning the inside of the chamber can be prevented.Type: GrantFiled: May 7, 2008Date of Patent: November 12, 2013Assignee: Sumco Techxiv CorporationInventors: Yasuhito Narushima, Fukuo Ogawa, Shinichi Kawazoe, Toshimichi Kubota
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Patent number: 8574363Abstract: After adding phosphorus (P) and germanium (Ge) into a silicon melt or adding phosphorus into a silicon/germanium melt, a silicon monocrystal is grown from the silicon melt by a Czochralski method, where a phosphorus concentration [P]L (atoms/cm3) in the silicon melt, a Ge concentration in the silicon monocrystal, an average temperature gradient Gave (K/mm) and a pull speed V (mm/min) are controlled to satisfy a formula (1) as follows, the phosphorus concentration [P] (atoms/cm3) in the silicon monocrystal is 4.84×1019 atoms/cm3 or more and 8.49×1019 atoms/cm3 or less, and the phosphorus concentration [P] (atoms/cm3) and the Ge concentration [Ge] (atoms/cm3) in the silicon monocrystal satisfy a relationship according to a formula (2) as follows while growing the silicon monocrystal. [P]L+(0.3151×[Ge]+3.806×1019)/1.5<0.5×(Gave/V+43)×1019??(1) [Ge]?6.95×[P]+5.90×1020??(2).Type: GrantFiled: May 23, 2008Date of Patent: November 5, 2013Assignee: Sumco Techxiv CorporationInventors: Shinichi Kawazoe, Yasuhito Narushima, Toshimichi Kubota, Fukuo Ogawa
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Patent number: 8573969Abstract: A silicon wafer preferable to a semiconductor device is produced by determining a heat treatment condition hardly causing slip dislocations and heat-treating the silicon wafer under the condition. The resistance is calculated by using a calculation formula used for predicting the slip resistance of the wafer from the density, size, and residual solid-solution oxygen concentration of the oxygen precipitation in the silicon wafer, the state of oxygen precipitation such that heat treatment not causing any slip dislocation can be carried out is designed, and thus a silicon wafer heat treatment method under the heat treatment condition not causing any slip dislocation is determined. A silicon wafer heat-treated under such a condition can be provided.Type: GrantFiled: September 28, 2007Date of Patent: November 5, 2013Assignee: Sumco TechXIV CorporationInventors: Shinya Sadohara, Kozo Nakamura, Shiro Yoshino
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Patent number: 8545712Abstract: In a method of manufacturing semiconductor wafers, front and back surfaces of the semiconductor wafers are simultaneously polished with a double-side polishing machine that includes: a carrier for accommodating the semiconductor wafer; and an upper press platen and a lower press platen for sandwiching the carrier. The method includes: accommodating the semiconductor wafer in the carrier while a thickness of the semiconductor wafer is set to be larger than a thickness of the carrier by 0 ?m to 5 ?m; and polishing the semiconductor wafer while feeding a polishing slurry to between the surfaces of the semiconductor wafer and surfaces of the press platens. In the polishing, an allowance of both surfaces of the semiconductor wafer is set at 5 ?m or less in total.Type: GrantFiled: September 11, 2008Date of Patent: October 1, 2013Assignee: Sumco Techxiv CorporationInventors: Hiroshi Takai, Kenji Satomura, Yuichi Nakayoshi, Katsutoshi Yamamoto, Kouji Mizowaki
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Patent number: 8535439Abstract: To provide a manufacturing method for a silicon single crystal that can reduce introduction of dislocation thereinto even if a required amount of dopant is added to a melt while growing a straight body portion of a silicon ingot. In a manufacturing method for a silicon single crystal according to the present invention that includes a dopant addition step of adding a dopant to a melt while a straight body portion of a silicon single crystal is growing in a growth step of growing the silicon single crystal by dipping a seed crystal into a silicon melt and then pulling the seed crystal therefrom, in the dopant addition step, a remaining mass of the melt is calculated at the beginning thereof, and the dopant is added to the melt at a rate of 0.01 to 0.035 g/min·kg per minute per 1 kg of the calculated remaining mass of the melt.Type: GrantFiled: January 8, 2010Date of Patent: September 17, 2013Assignee: Sumco Techxiv CorporationInventors: Yasuhito Narushima, Toshimichi Kubota, Shinichi Kawazoe, Fukuo Ogawa, Tomohiro Fukuda
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Patent number: 8518180Abstract: A silicon single crystal pull-up apparatus is used to pull up a doped silicon single crystal from a melt by means of the Czochralski process and includes a pull-up furnace, a sample chamber which is externally mounted on the pull-up furnace and houses a sublimable dopant, a shielding means for thermally isolating the interior of the pull-up furnace and the interior of the sample chamber, a sample tube which can be raised and lowered between the interior of the sample chamber and the interior of the pull-up furnace, and a raising and lowering means which is provided with guide rails on which the sample tube can slide and a wire mechanism by which the sample tube is raised and lowered along the guide rails.Type: GrantFiled: July 28, 2009Date of Patent: August 27, 2013Assignee: Sumco Techxiv CorporationInventors: Yasuhito Narushima, Shinichi Kawazoe, Fukuo Ogawa, Toshimichi Kubota, Tomohiro Fukuda
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Patent number: 8426297Abstract: A method of manufacturing a silicon wafer, an oxygen concentration in a surface layer to be maintained more than a predetermined value while promoting a defect-free layer. Strength of the surface layer can be made higher than that of an ordinary annealed sample as a COP free zone is secured. A method of manufacturing a silicon wafer doped with nitrogen and oxygen, includes growing a single crystal silicon doped with the nitrogen by Czochralski method, slicing the grown single crystal silicon to obtain a single crystal silicon wafer; heat treating the sliced single crystal silicon wafer in an ambient gas including a hydrogen gas and/or an inert gas; polishing the heat treated single crystal silicon wafer, after the heat treatment, such that an obtained surface layer from which COP defects have been removed by the heat treatment is polished away until an outermost surface has a predetermined oxygen concentration.Type: GrantFiled: August 7, 2009Date of Patent: April 23, 2013Assignee: Sumco Techxiv CorporationInventor: Shinya Sadohara
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Patent number: 8409347Abstract: In a dopant-injecting method for injecting a volatile dopant into a semiconductor melt, a doping device having an accommodating portion for accommodating a solid dopant and a cylindrical portion into which a gas ejected from the accommodating portion is introduced, a lower end surface of the cylindrical portion being opened to guide the gas to the melt, is used. The sublimation rate of the dopant in the accommodating portion is set in a range from 10 g/min to 50 g/min. Since a flow volume of the volatilized dopant gas is controlled by setting the sublimation rate of the dopant gas in the accommodating portion in the range from 10 g/min to 50 g/min, the melt is not blown off when the gas is blown onto the melt.Type: GrantFiled: July 20, 2007Date of Patent: April 2, 2013Assignee: Sumco TechXIV CorporationInventors: Shinichi Kawazoe, Yasuhito Narushima, Toshimichi Kubota
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Patent number: 8404046Abstract: A velocity of Ar gas flow passing through between a lower end of a cylindrical body and a thermal shielding body is influenced by arrangement of a pulling path of single crystal silicon, a cylindrical body, and a thermal shielding body. Accordingly, the velocity of the Ar gas flow passing through between a lower end of the cylindrical body and the thermal shielding body is controlled by adjusting a relative position of the pulling path of the single crystal silicon, the cylindrical body, and the thermal shielding body. As described above, dust falling off to silicon melt can be reduced, thereby preventing deterioration in quality of the single crystal silicon.Type: GrantFiled: June 27, 2006Date of Patent: March 26, 2013Assignee: Sumco Techxiv CorporationInventors: Makato Kamogawa, Koichi Shimomura, Yoshiyuki Suzuki, Daisuke Ebi
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Patent number: 8382895Abstract: A method of manufacturing a silicon monocrystal by FZ method, wherein a P-type or N-type silicon crystal having been pulled up by CZ method is used as a raw material. While impurities whose conductivity type is the same as that of the raw material are supplied by a gas doping method, the raw material is recrystallized by an induction-heating coil for obtaining a product-monocrystal.Type: GrantFiled: September 27, 2007Date of Patent: February 26, 2013Assignee: Sumco Techxiv CorporationInventors: Shinji Togawa, Toshiyuki Sato
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Patent number: 8372196Abstract: In a manufacturing apparatus for manufacturing an epitaxial wafer with a wafer being mounted substantially concentrically with a susceptor, a center rod is provided to extend in an up-and-down direction on a side of a non-mounting surface of the susceptor so that its upper end is adjacent to the center of the susceptor. With this arrangement, part of radiation light irradiated toward the susceptor is diffusely reflected by the center rod before reaching the central portion of the susceptor, thereby reducing the amount of the radiation light irradiated to the central portion of the susceptor as well as lowering the temperature of the portion. Since the center rod and the susceptor are not in surface contact, the center rod does not take the heat from the susceptor, thereby suppressing the temperature from decreasing locally at the central portion of the susceptor.Type: GrantFiled: November 2, 2009Date of Patent: February 12, 2013Assignee: Sumco Techxiv CorporationInventors: Motonori Nakamura, Yoshinobu Mori, Takeshi Masuda, Hidenori Kobayashi, Kazuhiro Narahara
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Patent number: 8361223Abstract: Provided is a method for reliably and easily measuring a liquid level by selecting an optimal reflection method from among a plurality of reflection methods, depending on growing conditions of a pulled single crystal. The method comprises: setting a plurality of measuring methods having different ways of determining the liquid level; creating, in advance, information that associates with a gap between the outer peripheral face of the single crystal and a predetermined position located between a heat shield and the outer peripheral face of the single crystal; determining the gap in accordance with manufacturing conditions; selecting a measuring method associated to the determined gap, on the basis of the information; and measuring the liquid level of a melt surface in use of the selected measuring method.Type: GrantFiled: July 18, 2008Date of Patent: January 29, 2013Assignee: Sumco Techxiv CorporationInventors: Toshio Hayashida, Ayumi Kihara, Takuaki Takami
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Patent number: 8334222Abstract: A processing method of a semiconductor wafer is provided. The method comprising the steps of: removing at least part of oxide film from a surface of the semiconductor wafer; removing liquid from the surface; and providing at least partial oxide film on the surface by applying an oxidizing gas wherein a gas flow of the oxidizing gas and/or an ambient gas involved by the oxidizing gas is characterized by an unsaturated vapor pressure of the liquid such that the liquid on the surface vaporizes. The above-described steps are conducted in this order.Type: GrantFiled: May 1, 2009Date of Patent: December 18, 2012Assignee: Sumco Techxiv CorporationInventors: Isamu Gotou, Tomonori Kawasaki
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Publication number: 20120305187Abstract: A method and an apparatus of etching a semiconductor wafer are provided. The etching apparatus of a semiconductor wafer having a marker inside includes: a monitoring device capable of monitoring a surface of the semiconductor wafer so as to detect the marker; a nozzle capable of jetting a mixed gas that contains hydrogen fluoride and ozone onto the surface of the semiconductor wafer; a regulator capable of adjusting at least one of hydrogen fluoride concentration and ozone concentration in the mixed gas; and a controller capable of determining whether the marker is detected by the monitoring device and terminating the etching process.Type: ApplicationFiled: August 15, 2012Publication date: December 6, 2012Applicant: SUMCO TECHXIV CORPORATIONInventors: Kazuaki Kozasa, Tomonori Kawasaki
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Patent number: 8303373Abstract: A diluted slurry supplying apparatus utilized in a polishing apparatus for finishing a semiconductor wafer with a slurry containing colloidal silica and water-soluble polymer is provided. The polishing method comprises: a slurry supplier capable of supplying the slurry containing the colloidal silica and the water-soluble polymer; a diluent supplier capable of supplying a diluent containing an aggregation preventing agent to dilute the slurry; a mixer capable of receiving the slurry and the diluent having been supplied from the slurry supplier and the diluent supplier, respectively, the mixer forming a diluted slurry with a pH value of at least 9; and an ultrasonic vibrator capable of applying an ultrasonic vibration to the diluted slurry staying in the mixer or being fed out from the mixer. Here, the diluent supplying apparatus can change a dilution proportion of the diluted slurry.Type: GrantFiled: May 22, 2009Date of Patent: November 6, 2012Assignee: Sumco Techxiv CorporationInventor: Kazuaki Kozasa
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Patent number: 8283241Abstract: A dopant device includes: a dopant holder that holds Ge which is solid at normal temperature and liquefies the Ge near a surface of the semiconductor melt, the dopant holder including a communicating hole for delivering the liquefied Ge downwardly; a cover portion for covering the Ge held by the dopant holder; and a vent provided on the cover portion for communicating with the outside. A dopant injecting method is carried out using such a dopant device, the dopant injecting method including: loading Ge dopant in a solid state into the doping device; liquefying the solid Ge dopant loaded into the doping device while holding the doping device at a predetermined height from a surface of a semiconductor melt; and doping the semiconductor melt with the liquefied Ge that is flowed from the communicating hole.Type: GrantFiled: May 23, 2008Date of Patent: October 9, 2012Assignee: Sumco Techxiv CorporationInventors: Yasuhito Narushima, Shinichi Kawazoe, Fukuo Ogawa, Toshimichi Kubota
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Patent number: 8273260Abstract: A method of etching a semiconductor wafer is provided. The method comprises the steps of: jetting a mixed gas including hydrogen fluoride and ozone onto a surface of a semiconductor wafer; monitoring the surface of the semiconductor wafer; analyzing the surface of the semiconductor wafer; and adjusting at least one of the hydrogen fluoride concentration and the ozone concentration in the mixed gas based on a result of the analysis.Type: GrantFiled: May 13, 2009Date of Patent: September 25, 2012Assignee: Sumco Techxiv CorporationInventors: Kazuaki Kozasa, Tomonori Kawasaki
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Patent number: 8251778Abstract: A double-side grinding apparatus is designed to be capable of minimizing thermal expansion of hydrostatic pad members and reducing nanotopography in performing wafer grinding. The double-side grinding apparatus is a double-side grinding apparatus for wafers that can simultaneously grind either surface of a wafer to be ground by pressing a grindstone against either surface of the wafer to be ground while hydrostatically supporting either surface of the wafer to be ground in a noncontact manner. Each hydrostatic supporting unit is formed with a hydrostatic pad member facing the wafer to be ground, and a base member placed on the back surface of the hydrostatic pad member. The hydrostatic pad member is made of a ceramic member, and the base member is made of a metal member.Type: GrantFiled: October 28, 2009Date of Patent: August 28, 2012Assignee: Sumco Techxiv CorporationInventor: Hiroyasu Futamura
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Patent number: 8241423Abstract: A semiconductor wafer for an epitaxial growth is disclosed comprising: a main face on which a vapor phase epitaxial layer grows; a back face provided on an opposite side of the wafer; a main chamfered part along a circumferential edge where the main face and a side face of the wafer meet; and a back chamfered part along a circumferential edge where the back face and the side face meet is provided. After a CVD layer formation process is conducted to form a layer at least on the back face and the back chamfered part, a machining process is conducted on the main face to remove a CVD layer at least partially formed thereon so as to polish the main face to a mirror finished surface with a maximum height of profile (Rz) not exceeding 0.3 ?m.Type: GrantFiled: September 28, 2007Date of Patent: August 14, 2012Assignee: Sumco Techxiv CorporationInventors: Eisyun Ikubo, Naoto Hirano, Moritaka Iwasa
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Patent number: 8216371Abstract: A Czochralski single crystal manufacturing apparatus uses multiple heaters to improve the controllability of crystal diameter. The power supplied to the multiple heaters is controlled so as to bring the pulling up speed close to a predetermined speed set value, and so as to bring the heater temperatures close to predetermined target temperature values. The ratio of electrical power between the heaters is controlled to agree with a predetermined power ratio set value which varies according to the crystal pulling up length, and the heater temperatures change along with this change, which causes disturbance to the diameter control. To compensate for this, heater temperature changes along with the power ratio set value change are taken into account in advance in the temperature set values. Accordingly, along with change of the power ratio set value, the temperature set values change to values appropriate for the current power ratio set value.Type: GrantFiled: July 20, 2007Date of Patent: July 10, 2012Assignee: Sumco Techxiv CorporationInventors: Tetsuhiro Iida, Shin Matsukuma