Patents Assigned to Sumco Techxiv Corporation
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Patent number: 8196545Abstract: In order to manufacture an epitaxial wafer having satisfactory flatness over its entire surface, epitaxial layers are experimentally grown upon actual wafer samples under various different layer formation conditions, the thickness profiles are measured over the entire surfaces of these wafers before and after growth of the layers, and, from the differences thereof, layer thickness profiles over the entire areas of the epitaxial layers under the various different layer formation conditions are ascertained and stored. Thereafter, the thickness profile of a substrate wafer is measured over its entire area, this is added to each of the layer thickness profiles under the various different layer formation conditions which have been stored, and the planarities of the manufactured wafers which would be manufactured under these various different layer formation conditions are predicted.Type: GrantFiled: April 20, 2009Date of Patent: June 12, 2012Assignee: Sumco Techxiv CorporationInventor: Yoshiaki Kurosawa
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Patent number: 8187383Abstract: In order to provide a semiconductor single crystal manufacturing device and a manufacturing method using a CZ method wherein the resistivity and oxygen concentration of a silicon single crystal can be controlled and wherein a single crystal yield can be improved, in the present invention, there is provided a wall 10 which defines a chamber inner wall 1c of a chamber 1, a crucible 2 and a heater 3. The wall 10 is formed by three members, namely, a single crystal side flow-straightening member 11, a melt surface side flow-straightening member 12 and a heater side flow-straightening member 13, which are connected to form a purge gas directing path 100. When the semiconductor single crystal is pulled, a flow speed of a purge gas that passes through the vicinity of the surface of the melt in a quartz crucible 3 is controlled.Type: GrantFiled: October 11, 2006Date of Patent: May 29, 2012Assignee: Sumco Techxiv CorporationInventors: Toshimichi Kubota, Eiichi Kawasaki, Tsuneaki Tomonaga, Shinichi Kawazoe
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Patent number: 8150784Abstract: A device controls an object in a time variant system with a dead time such as a Czochralski method single crystal production device (CZ equipment). The dead time, time constant, and process gain value of an object (CZ equipment) are set. The process gain preset value has time variant characteristics. An output value and its first-order and second-order time differentiated values serve as the state variable. A nonlinear state predicting unit predicts a state variable value at a future time, based upon the current output value, dead time, time constant, and process gain preset value. A gain scheduled sliding mode control unit performs a gain scheduled sliding mode control operation based upon the state variable value at the future time, an output deviation at the future time, the time constant, and the set value of the process gain at the future time, to determine the manipulated variable of the object.Type: GrantFiled: June 7, 2006Date of Patent: April 3, 2012Assignee: Sumco Techxiv CorporationInventors: Kenichi Bandoh, Shigeo Morimoto, Takuji Okumura, Tetsu Nagata, Masaru Shimada, Junsuke Tomioka, Yutaka Shiraishi, Takeshi Kodama
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Patent number: 8130386Abstract: This invention provides a position measuring method for measuring a surface level of melt in a crucible arranged in the inside of a Czochralski furnace based on a principle of triangulation, in which a light source and a photo detector are provided; light emitted from the light source is applied to the surface of the melt; and the light reflected by the surface of the melt is received by the photo detector, the method comprising: providing a member in the vicinity of the surface of the melt; and causing the emitted light to be reflected by the member, applying the reflected light to the surface of the melt, and causing the light reflected by the surface of the melt to be received by the photo detector.Type: GrantFiled: November 2, 2006Date of Patent: March 6, 2012Assignee: Sumco Techxiv CorporationInventors: Toshio Hayashida, Naoji Mitani, Ayumi Kihara
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Patent number: 8115908Abstract: While position measurement of an edge position of a thermal shield takes place in a short time with high working efficiency, the edge position can be measured accurately without variation. First determination takes place while a distance is measured with a first scanning interval. When a change in a measured distance which can be determined as the edge position is determined as a result, an optical scanning position is returned by a predetermined amount reversely to the scanning direction (or reversely to the scanning direction), and while laser beam is scanned again from the returned optical scanning position, second determination takes place while measuring the distance with a second scanning interval shorter than the first scanning interval.Type: GrantFiled: August 25, 2008Date of Patent: February 14, 2012Assignee: Sumco Techxiv CorporationInventors: Toshio Hayashida, Ayumi Kihara, Naoji Mitani
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Patent number: 8110042Abstract: Using a pulling-up apparatus, an oxygen concentration of the monocrystal at a predetermined position in a pulling-up direction is controlled based on a relationship in which the oxygen concentration of the monocrystal is decreased as a flow rate of the inactive gas at a position directly above a free surface of the dopant-added melt is increased when the monocrystal is manufactured with a gas flow volume in the chamber being in the range of 40 L/min to 400 L/min and an inner pressure in the chamber being in the range of 5332 Pa to 79980 Pa. Based on the relationship, oxygen concentration is elevated to manufacture the monocrystal having a desirable oxygen concentration. Because the oxygen concentration is controlled under a condition corresponding to a condition where the gas flow rate is rather slow, the difference between a desirable oxygen concentration profile of the monocrystal and an actual oxygen concentration profile is reduced.Type: GrantFiled: May 7, 2008Date of Patent: February 7, 2012Assignee: Sumco Techxiv CorporationInventors: Yasuhito Narushima, Shinichi Kawazoe, Fukuo Ogawa, Tsuneaki Tomonaga, Yasuyuki Ohta, Toshimichi Kubota, Shinsuke Nishihara
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Patent number: 8045150Abstract: A semiconductor wafer inspection method includes: an imaging step in which a first image being an image of the chamfered surface seen from the main surface side and a second image being an image of the chamfered surface seen from the back surface side are taken; a calculation step in which a first width is obtained based on the first image, the first width being a width of the chamfered surface seen from the main surface side, a second width is obtained based on the second image, the second width being a width of the chamfered surface seen from the back surface side, and a ratio of the first width to the second width thus obtained is calculated; and a shape determination step in which a form of the chamfered surface is determined to be abnormal in a case where the ratio is out of a predetermined range.Type: GrantFiled: September 8, 2009Date of Patent: October 25, 2011Assignee: Sumco Techxiv CorporationInventors: Kantarou Torii, Kouichi Imura
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Patent number: 8043428Abstract: In growing a silicon monocrystal from a silicon melt added with an N-type dopant by Czochralski method, the monocrystal is grown such that a relationship represented by a formula (1) as follows is satisfied. In the formula (1): a dopant concentration in the silicon melt is represented by C (atoms/cm3); an average temperature gradient of the grown monocrystal is represented by Gave(K/mm); a pulling-up speed is represented by V (mm/min); and a coefficient corresponding to a kind of the dopant is represented by A. By growing the silicon monocrystal under a condition shown in the left to a critical line G1, occurrence of abnormal growth due to compositional supercooling can be prevented.Type: GrantFiled: May 23, 2008Date of Patent: October 25, 2011Assignee: Sumco Techxiv CorporationInventors: Shinichi Kawazoe, Toshimichi Kubota, Yasuhito Narushima, Fukuo Ogawa
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Patent number: 8021484Abstract: A method of forming an epitaxial layer to increase flatness of an epitaxial silicon wafer is provided. In particular, a method of controlling the epitaxial layer thickness in a peripheral part of the wafer is provided. An apparatus for manufacturing an epitaxial wafer by growing an epitaxial layer with reaction of a semiconductor wafer and a source gas in a reaction furnace comprising: a pocket in which the semiconductor wafer is placed; a susceptor fixing the semiconductor; orientation-dependent control means dependent on a crystal orientation of the semiconductor wafer and/or orientation-independent control means independent from the crystal orientation of the semiconductor wafer, wherein the apparatus may improve flatness in a peripheral part of the epitaxial layer.Type: GrantFiled: March 30, 2007Date of Patent: September 20, 2011Assignee: Sumco Techxiv CorporationInventors: Kazuhiro Narahara, Hirotaka Kato, Koichiro Hayashida
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Patent number: 7993452Abstract: A role of a bottom face of a silicon wafer is identified in a manufacturing process of the silicon wafer. And preferable characteristic feature is also identified. In order to obtain the above characteristic feature, a process method to be implemented into the method of manufacturing a normal silicon wafer is provided. For example, the method comprises: a pre-cleaning process for cleaning the silicon wafer having top and bottom faces processed to a mirror finish; and a rapid thermal process or an epitaxial growth process, wherein the pre-cleaning process comprises a hydrofluoric acid (HF) process and a subsequent pure water (DIW) process.Type: GrantFiled: March 30, 2007Date of Patent: August 9, 2011Assignee: Sumco Techxiv CorporationInventors: Koichiro Hayashida, Kazuhiro Narahara, Hirotaka Kato
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Publication number: 20110140241Abstract: A process for production of a silicon ingot, by which a silicon ingot exhibiting a low resistivity even in the top portion can be produced. The process for the production of a silicon ingot comprises includes withdrawing a silicon seed crystal (13) from a silicon melt (11) to grow a silicon single crystal (12), with the silicon seed crystal (13) and the silicon melt (11) containing dopants of the same kind.Type: ApplicationFiled: August 11, 2009Publication date: June 16, 2011Applicants: SUMCO TECHXIV CORPORATION, SUMCO CORPORATIONInventors: Shinichi Kawazoe, Toshimichi Kubota, Fukuo Ogawa, Yasuhito Narushima
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Publication number: 20110143526Abstract: A method of manufacturing a silicon wafer, an oxygen concentration in a surface layer to be maintained more than a predetermined value while promoting a defect-free layer. Strength of the surface layer can be made higher than that of an ordinary annealed sample as a COP free zone is secured. A method of manufacturing a silicon wafer doped with nitrogen and oxygen, includes growing a single crystal silicon doped with the nitrogen by Czochralski method, slicing the grown single crystal silicon to obtain a single crystal silicon wafer; heat treating the sliced single crystal silicon wafer in an ambient gas including a hydrogen gas and/or an inert gas; polishing the heat treated single crystal silicon wafer, after the heat treatment, such that an obtained surface layer from which COP defects have been removed by the heat treatment is polished away until an outermost surface has a predetermined oxygen concentration.Type: ApplicationFiled: August 7, 2009Publication date: June 16, 2011Applicant: SUMCO TECHXIV CORPORATIONInventor: Shinya Sadohara
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Publication number: 20110132257Abstract: A silicon single crystal pull-up apparatus is used to pull up a doped silicon single crystal from a melt by means of the Czochralski process and includes a pull-up furnace, a sample chamber which is externally mounted on the pull-up furnace and houses a sublimable dopant, a shielding means for thermally isolating the interior of the pull-up furnace and the interior of the sample chamber, a sample tube which can be raised and lowered between the interior of the sample chamber and the interior of the pull-up furnace, and a raising and lowering means which is provided with guide rails on which the sample tube can slide and a wire mechanism by which the sample tube is raised and lowered along the guide rails.Type: ApplicationFiled: July 28, 2009Publication date: June 9, 2011Applicant: SUMCO TECHXIV CORPORATIONInventors: Yasuhito Narushima, Shinichi Kawazoe, Fukuo Ogawa, Toshimichi Kubota, Tomohiro Fukuda
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Publication number: 20110120367Abstract: A silicon single crystal pull-up apparatus includes a pull-up furnace, a sample chamber in which a sublimable dopant is housed, a sample tube which can be raised and lowered between the interior of the sample chamber and the interior of the pull-up furnace, a raising and lowering means for raising and lowering the sample tube, a supply pipe which is installed inside the pull-up furnace and supplies the sublimable dopant to a melt, and a connection means for connecting the sample tube and the supply pipe. The connection means is constructed from a ball joint structure comprising a convex member which projects from one end of the sample tube and a concave member which is provided at one end of the supply pipe and is formed to be engageable with the convex member. The contact surfaces of the convex member and the concave member are formed to be curved surfaces.Type: ApplicationFiled: July 28, 2009Publication date: May 26, 2011Applicant: SUMCO TECHXIV CORPORATIONInventors: Yasuhito Narushima, Shinichi Kawazoe, Fukuo Ogawa, Toshimichi Kubota, Tomohiro Fukuda
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Patent number: 7920999Abstract: Internal gettering behavior in a silicon substrate is predicted by using an arithmetic expression established among an initial iron contamination concentration Cini in the silicon substrate, a density N of oxygen precipitates, a radius R of the oxygen precipitates, internal gettering heat treatment temperature T, internal gettering heat treatment time t, and a concentration C(t) of iron (Fe) remaining in the silicon substrate after a heat treatment. In the prediction of internal gettering behavior in the silicon substrate, an arithmetic expression is added considering a process in which nuclei of a contaminant heavy metal silicide are generated on the surface of the oxygen precipitates, and a process in which the contaminant heavy metal is gettered by the oxygen precipitates having the contaminant heavy metal silicide nuclei generated on the surface thereof. This invention is also applicable for internal gettering of a contaminant heavy metal other than iron (Fe), such as copper (Cu), nickel (Ni) or the like.Type: GrantFiled: June 5, 2006Date of Patent: April 5, 2011Assignee: Sumco Techxiv CorporationInventor: Kozo Nakamura
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Patent number: 7918934Abstract: A single crystal semiconductor manufacturing apparatus in which the concentration of oxygen in a single crystal semiconductor is controlled while pulling up a single crystal semiconductor such as single crystal silicon by the CZ method, a single crystal semiconductor manufacturing method, and a single crystal ingot manufactured by the method are disclosed. The natural convection (20) in the melt (5) in a quartz crucible (3) is controlled by regulating the temperatures at a plurality of parts of the melt (5). A single crystal semiconductor (6) can have a desired diameter by regulating the amount of heat produced by heating means (9a) on the upper side. Further the ratio between the amount of heat produced by the upper-side heating means (9a) and that by the lower-side heating means (9b) is adjusted to vary the process condition. In the adjustment, the amount of heat produced by the lower-side heating means (9b) is controlled to a relatively large proportion.Type: GrantFiled: November 29, 2006Date of Patent: April 5, 2011Assignee: Sumco Techxiv CorporationInventors: Yutaka Shiraishi, Jyunsuke Tomioka, Takuji Okumura, Tadayuki Hanamoto, Takehiro Komatsu, Shigeo Morimoto
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Publication number: 20110017948Abstract: Disclosed is a silicon single crystal pull-up apparatus that can grow a silicon single crystal having a desired electrical resistivity, to which a sublimable dopant has been reliably added, regardless of the length of the time necessary for the formation of a first half part of a straight body part in a silicon single crystal. Also disclosed is a process for producing a silicon single crystal. The silicon single crystal pull-up apparatus pulls up a silicon single crystal from a melt by a Czochralski method. The silicon single crystal pull-up apparatus comprises a pull-up furnace, a sample chamber that is externally mounted on the pull-up furnace and houses a sublimable dopant, a shielding mechanism that thermally shields the pull-up furnace and the sample chamber, and supply means that, after the release of shielding of the shielding mechanism, supplies the sublimable dopant into the melt.Type: ApplicationFiled: March 5, 2009Publication date: January 27, 2011Applicant: SUMCO TECHXIV CORPORATIONInventor: Tomohiro Fukuda
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Patent number: 7875116Abstract: A method in which SSDs are reliably reduced while reducing void defects other than the SSDs on a wafer surface, which is essential for an annealed wafer, and ensuring that BMDs serving as gettering source in a bulk are generated, in order to stabilize the quality of the annealed wafer. Considering that annealing a silicon wafer leads to an increase of density (quantity) of deposits associated with oxygen and nitrogen and forming a core of the SSDs, SSDs are decreased by reducing the density (quantity) of the deposits associated with oxygen and nitrogen by controlling three parameters of oxygen concentration, nitrogen concentration and cooling concentration during the process of pulling and growing the silicon single crystal 6 before annealing. Alternatively, SSD is reduced by polishing after annealing.Type: GrantFiled: February 14, 2006Date of Patent: January 25, 2011Assignee: Sumco Techxiv CorporationInventors: Shinya Sadohara, Ryota Suewaka, Shiro Yoshino, Kozo Nakamura, Yutaka Shiraishi, Syunji Nonaka
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Patent number: 7875117Abstract: An epitaxial wafer and a high-temperature heat treatment wafer having an excellent gettering capability are obtained by performing epitaxial growth or a high-temperature heat treatment. A relational equation relating the density to the radius of an oxygen precipitate introduced in a silicon crystal doped with nitrogen at the time of crystal growth can be derived from the nitrogen concentration and the cooling rate around 1100° C. during crystal growth, and the oxygen precipitate density to be obtained after a heat treatment can be predicted from the derived relational equation relating the oxygen precipitate density to the radius, the oxygen concentration, and the wafer heat treatment process. Also, an epitaxially grown wafer and a high-temperature annealed wafer whose oxygen precipitate density has been controlled to an appropriate density are obtained, using conditions predicted by the method.Type: GrantFiled: August 11, 2005Date of Patent: January 25, 2011Assignee: Sumco Techxiv CorporationInventors: Kouzo Nakamura, Susumu Maeda, Kouichirou Hayashida, Takahisa Sugiman, Katsuhiko Sugisawa
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Publication number: 20100294999Abstract: The sublimation speed of dopant can be precisely controlled without being influenced by a change over time of intra-furnace thermal environment. A dopant supply unit equipped with an accommodation chamber and a supply tube is provided. A sublimable dopant is accommodated. Upon sublimation of the dopant within the accommodation chamber, the sublimed dopant is introduced into a melt. The dopant within the accommodation chamber of the dopant supply unit is heated. The amount of heating by means of heating means is controlled so as to sublime the dopant at a desired sublimation speed. The dopant is supplied to the melt so that the dopant concentration until the first half of a straight body portion of the silicon single crystal is in the state of low concentration or non-addition.Type: ApplicationFiled: April 23, 2008Publication date: November 25, 2010Applicant: SUMCO TECHXIV CORPORATIONInventors: Yasuhito Narushima, Shinichi Kawazoe, Fukuo Ogawa, Masahiro Irokawa, Toshimichi Kubota