Patents Assigned to Sumitomo Electric Device Innovations, Inc.
  • Patent number: 11011370
    Abstract: A method for manufacturing a semiconductor device includes: forming an ohmic electrode including Al on a semiconductor substrate; forming a SiN film covering the ohmic electrode; forming a first photoresist on the SiN film, the first photoresist having an opening pattern overlapping the ohmic electrode; performing ultraviolet curing of the first photoresist; forming an opening in the SiN film exposed through the opening pattern and causing a surface of the ohmic electrode to be exposed inside the opening; forming a barrier metal layer on the first photoresist and on the ohmic electrode exposed through the opening; forming a second photoresist in the opening pattern; performing a heat treatment on the second photoresist and covering the barrier metal layer overlapping the opening with the second photoresist; and etching the barrier metal layer using the second photoresist.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: May 18, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Kenichi Watanabe
  • Publication number: 20210143002
    Abstract: A semiconductor device is made by: forming an ohmic electrode including Al on a semiconductor substrate; forming a SiN film covering the ohmic electrode; forming a first photoresist on the SiN film, the first photoresist having an opening pattern overlapping the ohmic electrode; performing ultraviolet curing of the first photoresist; forming an opening in the SiN film exposed through the opening pattern and causing a surface of the ohmic electrode to be exposed inside the opening; forming a barrier metal layer on the first photoresist and on the ohmic electrode exposed through the opening; forming a second photoresist in the opening pattern; performing a heat treatment on the second photoresist and covering the barrier metal layer overlapping the opening with the second photoresist; and etching the barrier metal layer using the second photoresist.
    Type: Application
    Filed: January 21, 2021
    Publication date: May 13, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Kenichi WATANABE
  • Publication number: 20210134739
    Abstract: A semiconductor device including a base, a buffer member, a frame, a lid, and a semiconductor element, is disclosed. The ceramic frame is mounted on the copper base with the molybdenum buffer member interposed therebetween. The semiconductor element is sealed in a space within the frame defined by the lid. The frame includes a top portion, a lower stage portion that is disposed below the top portion and is provided with an input electrode and an output electrode, and an upper stage portion. The upper stage portion is formed in an arrangement direction of the input electrode and the output electrode, and is formed below the top portion and above the lower stage portion. The upper stage portion includes an upper stage connection portion formed on the periphery of the lower stage portion in a direction intersecting the arrangement direction of the input electrode and the output electrode.
    Type: Application
    Filed: December 18, 2020
    Publication date: May 6, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Tuneyuki TANAKA
  • Patent number: 10998243
    Abstract: A method of manufacturing a semiconductor device includes forming a field plate on an insulating film covering a transistor, the field plate being electrically coupled to a gate of the transistor via the insulating film, and the transistor being located on a substrate, forming a silicon nitride protective film covering the insulating film and the field plate, forming a silicon oxide base film on the silicon nitride protective film, and forming a MIM capacitor on the silicon oxide base film. The MIM capacitor includes a first electrode, a dielectric film and a second electrode which are stacked in an order. Forming the MIM capacitor includes performing wet etching on the silicon oxide base film on the field plate after forming the dielectric film.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: May 4, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Takuma Nakano, Tomoki Maruyama
  • Publication number: 20210126596
    Abstract: An amplifier device includes a substrate, a composite packaged amplifier having a bottom plate and an output plate, a first amplifier and a second amplifier provided on the bottom plate, a combining node that combines an output of the first amplifier with an output of the second amplifier, an output matching circuits provided on the bottom plate, that has a first transmission line provided between the first amplifier and the combining node, and a second transmission line provided between the combining node and the second amplifier, a third transmission line having one transmission line on which the output plate is mounted and other transmission line that connects the one transmission line to the external port, and wirings connecting to one terminal of the output plate and the combining node. A length of the output plate and the other transmission line is equal or less than ?/4 radian for a signal.
    Type: Application
    Filed: October 26, 2020
    Publication date: April 29, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: James WONG
  • Patent number: 10985525
    Abstract: The transmitter module including a semiconductor laser chip, a first carrier, a second carrier, and a lens is disclosed. The first carrier mounts the semiconductor laser chip thereon. The second carrier includes a first surface, a second surface, and a connection surface connecting the first surface with the second surface. The first surface faces in a first direction intersecting an axis direction of the chip to mount the first carrier thereon. The second surface faces in the first direction and is provided at a position farther away from the axis of the chip than the first surface. The lens is fixed to the second surface by an adhesive resin. The connection surface is set back far from a front end of the first carrier adjacent to an emission end of the chip toward a back end of the first carrier opposite to the front end in the axis direction.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: April 20, 2021
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Toshiaki Kihara
  • Publication number: 20210111268
    Abstract: A nitride semiconductor device is disclosed. The semiconductor device is formed by a process that first deposits a silicon nitride (SiN) film on a semiconductor layer by the lower pressure chemical vapor deposition (LPCVD) technique at a temperature, then, forming an opening in the SiN film for an ohmic electrode. Preparing a photoresist on the SiN film, where the photoresist provides an opening that fully covers the opening in the SiN film, the process exposes a peripheral area around the opening of the SiN film to chlorine (Cl) plasma that may etch the semiconductor layer to form a recess therein. Metals for the ohmic electrode are filled within the recess in the semiconductor layer and the peripheral area of the SiN film. Finally, the metals are alloyed at a temperature lower than the deposition temperature of the SiN film.
    Type: Application
    Filed: October 30, 2020
    Publication date: April 15, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Takuma NAKANO
  • Publication number: 20210111278
    Abstract: A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Ken NAKATA
  • Patent number: 10978375
    Abstract: A semiconductor device comprising a metal base, a metal frame, a semiconductor element, a feedthrough, and a metal side plate is disclosed. The semiconductor element is mounted on the metal base in a space defined by the metal base and the metal frame. The feedthrough is inserted into a cutout of the metal frame, and includes a wiring, a lower block mounting the wiring thereon, and an upper block mounted on the lower block. A combined sectional shape of the lower block and the upper block is a projecting shape. A part of the upper block is located inside the space. The metal side plate is provided between a side surface of the feedthrough and the cutout of the metal frame. The metal side plate has a projecting shape and covers the entire side surface of the feedthrough.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: April 13, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Akitada Kodama, Masato Furukawa
  • Patent number: 10978569
    Abstract: A process of forming a nitride semiconductor device is disclosed. The process first deposits a silicon nitride (SiN) film on a semiconductor layer by the lower pressure chemical vapor deposition (LPCVD) technique at a temperature, then, forming an opening in the SiN film for an ohmic electrode. Preparing a photoresist on the SiN film, where the photoresist provides an opening that fully covers the opening in the SiN film, the process exposes a peripheral area around the opening of the SiN film to chlorine (Cl) plasma that may etch the semiconductor layer to form a recess therein. Metals for the ohmic electrode are filled within the recess in the semiconductor layer and the peripheral area of the SiN film. Finally, the metals are alloyed at a temperature lower than the deposition temperature of the SiN film.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: April 13, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Takuma Nakano
  • Publication number: 20210104977
    Abstract: A semiconductor amplifier 1 includes transistors 21a and 21b mounted side by side on a bottom plate 2 in a space in a package 6, a matching circuit 22a mounted between the transistors 21a, 21b on the bottom plate 2, a matching circuit 22b mounted on an opposite side of the transistor 21b from the transistor 21a on the bottom plate 2, an input terminal TIN installed on one side of a wiring substrate 3, an output terminal TOUT installed on the other side of the wiring substrate 3, and gate bias terminals T1G and T2G and drain bias terminals T1N and T2D installed at positions with the input terminal TIN and the output terminal TOUT of the wiring substrate 3, and the transistor 21a, the matching circuit 22a, the transistor 21b, and the matching circuit 22b are linearly placed between the input terminal TIN and the output terminal TOUT.
    Type: Application
    Filed: December 17, 2020
    Publication date: April 8, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Naoyuki MIYAZAWA
  • Publication number: 20210104437
    Abstract: A semiconductor device includes a field plate on an insulating film covering a transistor, the field plate being electrically coupled to a gate of the transistor via the insulating film, and the transistor being located on a substrate, a silicon nitride protective film covering the insulating film and the field plate, a silicon oxide base film on the silicon nitride protective film, and a MIM capacitor on the silicon oxide base film. The MIM capacitor includes a first electrode, a dielectric film and a second electrode which are stacked in an order. The MIM capacitor is formed by performing wet etching on the silicon oxide base film on the field plate after the dielectric film is formed.
    Type: Application
    Filed: November 23, 2020
    Publication date: April 8, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Takuma NAKANO, Tomoki MARUYAMA
  • Publication number: 20210104610
    Abstract: A semiconductor device includes a substrate, an active region and an inactive region surrounding the active region, a gate electrode, a drain electrode and a source electrode on the active region, a drain interconnection including a drain finger and a drain bar, and a source interconnection including a source finger and a source bar. The source bar is located on an opposite side of the drain bar across the active region in a first direction. The source electrode includes a first side facing the drain bar in the first direction and a first depression in a middle of the first side. A first depth of the first depression in the first direction is equal or more than a first interval between the drain bar and the first side in the first direction.
    Type: Application
    Filed: December 16, 2020
    Publication date: April 8, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Chihoko AKIYAMA
  • Patent number: 10971614
    Abstract: A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: April 6, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Ken Nakata
  • Publication number: 20210098523
    Abstract: An optical semiconductor device includes a semiconductor light receiving element, a capacitor, and a carrier. The carrier has a mounting surface on which the semiconductor light receiving element and the capacitor are mounted. The optical semiconductor device includes a first conductive pattern including a first mounting area and a first bonding pad, a second conductive pattern including a second mounting area and a third mounting area, and a third conductive pattern including a second bonding pad. The first mounting area is connected to a first electrode of the semiconductor light receiving element. The second mounting area is connected to a second electrode of the semiconductor light receiving element. The third mounting area is connected to one electrode of the capacitor. The conductive patterns are separated from each other. The other electrode of the capacitor is electrically connected to the third conductive pattern via a wire.
    Type: Application
    Filed: September 18, 2020
    Publication date: April 1, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Kyohei MAEKAWA
  • Publication number: 20210091023
    Abstract: A semiconductor device is made by a manufacturing method that includes forming an organic insulating layer on a semiconductor on which metal wiring is provided, the organic insulating layer having an opening to expose part of the metal wiring, forming a seed metal covering the part of the metal wiring exposed from the opening, and an inside face and an around portion of the opening of the organic insulating layer, forming a mask covering an edge of the seed metal and exposing part of the seed metal formed in the opening, and forming a barrier metal on the seed metal exposed from the mask by electroless plating. The mask includes an organic material or an inorganic dielectric material.
    Type: Application
    Filed: November 18, 2020
    Publication date: March 25, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Keita MATSUDA
  • Patent number: 10957591
    Abstract: A process of forming a semiconductor device is disclosed, where the semiconductor device provides a substrate. The process includes steps of: (a) depositing a first metal layer containing nickel (Ni) on a secondary surface of the substrate and within a substrate via provided in the substrate; (b) depositing a second metal layer on the first metal layer by electrolytic plating; (c) depositing a third metal layer on the second metal layer, where the third metal layer contains at least one of Ni and titanium (Ti); (d) exposing the second metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the third metal layer; and (e) die-bonding the semiconductor device on an assembly substrate by interposing solder between the secondary surface of the substrate and the assembly substrate.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 23, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Toshiyuki Kosaka, Shunsuke Kurachi
  • Patent number: 10957613
    Abstract: A semiconductor module includes a base plate made of a metal, an insulating frame provided on a peripheral edge portion of the base plate, a lead made of a metal and provided on the frame, and a semiconductor device mounted on the base plate in a space surrounded by the frame, wherein the frame is fixed to the base plate by a bonding material containing silver, the frame has concave portions formed in an inner portion which is a corner portion on a space side and an outer portion which is a corner portion on a side opposite to the inner portion in a surface thereof which faces the base plate, and the concave portions are filled with a coating material.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: March 23, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Tomoki Ohno
  • Publication number: 20210083355
    Abstract: A variable attenuator is an attenuator which is formed by coupling two transmission lines having an electrical length of ?/4 corresponding to a wavelength ? of an input signal, has one end of one transmission line as an input terminal, has the other end of the one transmission line as a through terminal, has one end of the other transmission line as a coupling terminal and has the other end of the other transmission line as an output terminal, wherein the variable attenuator has a resistor pair having the same impedance at both the through terminal and the coupling terminal, and has a resistor pair having the same impedance at both the input terminal and the output terminal.
    Type: Application
    Filed: December 1, 2020
    Publication date: March 18, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Akio OYA
  • Publication number: 20210083158
    Abstract: An optical semiconductor device includes: a mesa that is provided on a surface in a <011> direction of a semiconductor substrate having a (100) plane orientation and being of a first conductivity type, and includes a first cladding layer of the first conductivity type, an active layer, and a second cladding layer of a second conductivity type; a semi-insulating buried layer that buries both sides of the mesa, is provided on the semiconductor substrate, and includes a first region and a second region farther from the mesa than the first region; an insulation film provided on the first and second regions of the buried layer; and an electrode provided on the mesa and the insulation film on the first region; wherein a surface of the first region is at a height equal to or lower than a surface of the mesa, and lowers at farther distances from the mesa.
    Type: Application
    Filed: September 14, 2020
    Publication date: March 18, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Kan TAKADA