Abstract: An optical semiconductor device includes a chassis that has an external wall, a feedthrough that penetrates the external wall of the chassis and has a projection portion projecting toward outside of the chassis from the external wall, a connection terminal that is electrically connected to a component mounted in the chassis and is on the projection portion of the feedthrough, a first temperature detector that is on an external face of the external wall of the chassis and detects a temperature of the chassis, and a flexible substrate of which an end is connected to the connection terminal and of which a portion spaced from the end is connected to the first temperature detector, wherein the first temperature detector is between the external wall and the flexible substrate.

Abstract: A high frequency amplifier 1 includes an input terminal PIN, an output terminal POUT, a transistor 5 configured to amplify an RF signal applied to the input terminal PIN, a matching circuit 9 for a fundamental of the RF signal and a reflection circuit 7 for a harmonic relative to the fundamental, the matching circuit 9 and the reflection circuit 7 being connected in series between the transistor 5 and the output terminal POUT, an extraction circuit 13 configured to extract a harmonic appearing at the output terminal POUT, processing circuits 15, 17 configured to adjust a phase and intensity of the harmonic extracted by the extraction circuit 13, and a multiplexing circuit 19 configured to multiplex the harmonic processed by the processing circuits 15, 17 to the harmonic reflected by the reflection circuit 7 and give the multiplexed harmonic to the transistor 5.

Abstract: A semiconductor light receiving element includes a first semiconductor layer, a waveguide type photodiode structure, an optical waveguide structure, and a fourth semiconductor layer. The waveguide type photodiode structure is provided on the first semiconductor layer. The waveguide type photodiode structure includes an optical absorption layer, a second semiconductor layer, a multiplication layer, and a third semiconductor layer. The optical waveguide structure is provided on the first semiconductor layer. The optical waveguide structure includes an optical waveguiding core layer and a cladding layer. An end face of the waveguide type photodiode structure faces to an end face of the optical waveguide structure. The fourth semiconductor layer is located between the end face of the waveguide type photodiode structure and the end face of the optical waveguide structure. The fourth semiconductor layer is contacted with the multiplication layer of the end face of the waveguide type photodiode structure.

Abstract: A first semiconductor layer is of a first conductive type. A multiplication layer is of a first conductive type and is provided on the first semiconductor layer. An optical waveguide structure has an end face provided on a first region of the multiplication layer. A photodiode structure has an end face and provided on a second region of the multiplication layer. The photodiode structure has a third semiconductor layer being of a second conductive type, an optical absorption layer being of an intrinsic conductive type or of a second conductive type, and a second semiconductor layer being of a second conductive type which are arranged in this order. The optical waveguide structure includes an optical waveguiding core layer and a cladding layer. The end face of the waveguide type photodiode structure and the end face of the optical waveguide structure are in contact.

Abstract: A method of controlling an optical amplifying system that processes an optical signal with the PAM4 mode is disclosed. The optical amplifying system includes a variable optical attenuator (VOA) and a semiconductor optical amplifier (SOA). The VOA attenuates the optical signal such that a maximum optical power thereof corresponding to one of the physical levels of the PAM4 signal becomes equal to a preset optical level for which the SOA may be linearly operable. The SOA may amplify the thus attenuated optical signal with a fixed optical gain.

Abstract: Provided is an optical semiconductor device including: a wavelength tunable laser element; a beam splitter that splits an outgoing beam of the wavelength tunable laser element into a first light beam and a second light beam parallel to each other, and outputs the first light beam and the second light beam; and an etalon that transmits the first light beam and the second light beam, wherein an optical path length to the first light beam of the etalon is different from an optical path length to the second light beam of the etalon.

Abstract: A method is disclosed for manufacturing a semiconductor device including a mounting substrate, a semiconductor chip, a rear-surface metal layer, an AuSn solder layer, and a solder blocking metal layer, is disclosed. The semiconductor chip is mounted on the mounting substrate, and includes front and rear surfaces, and a heat generating element. The rear-surface metal layer includes gold (Au). The AuSn solder layer is located between the mounting substrate and the rear surface to fix the semiconductor chip to the mounting substrate. The solder blocking metal layer is located between the rear surface and the mounting substrate, and in a non-heating region excluding a heating region in which the heat generating element is formed. The solder blocking metal layer includes at least one of NiCr, Ni and Ti and extends to an edge of the semiconductor chip. A void is provided between the solder blocking metal layer and the AuSn solder layer.

Abstract: An optical semiconductor element including a semiconductor substrate, a first cladding layer of a first conductive type provided on the semiconductor substrate, an active layer provided on the first cladding layer, a second cladding layer of a second conductive type provided on the active layer, a first mesa constituted of a part of the first cladding layer, the active layer, and the second cladding layer, an auxiliary cladding layer of the second conductive type provided on the first mesa, a second mesa constituted of the auxiliary cladding layer, and a semi-insulating layer provided on the first cladding layer and on both sides of the first mesa and both sides of the second mesa, wherein a width of the second mesa is greater than a width of the first mesa.

Abstract: A field effect transistor includes: a semiconductor region including a first inactive region, an active region, and a second inactive region arranged side by side in a first direction; a gate electrode, a source electrode, and a drain electrode on the active region; a gate pad on the first inactive region; a gate guard on and in contact with the semiconductor region, the gate guard being apart from the gate pad and located between an edge on the first inactive region side of the semiconductor region and the gate pad; a drain pad on the second inactive region; a drain guard on and in contact with the semiconductor region, the drain guard being apart from the drain pad and located between an edge on the second inactive region side of the semiconductor region and the drain pad; and a metal film electrically connected to the gate guard.

Abstract: A semiconductor device includes at least one transistor, a plurality of input wires, and a plurality of output wires. The at least one transistor has a plurality of input pads arranged along one side of the at least one transistor and a plurality of output pads arranged along another side of the at least one transistor facing the one side. The plurality of input wires are respectively connected to the plurality of input pads. The plurality of output wires are respectively connected to the plurality of output pads and have longer wire lengths than the plurality of input wires. Adjacent input wires of the plurality of input wires are arranged parallel to each other, and adjacent output wires of the plurality of output wires are arranged non-parallel to each other.

Abstract: A semiconductor device manufacturing method includes forming an organic insulating layer on a semiconductor on which metal wiring is provided, the organic insulating layer having an opening to expose part of the metal wiring, forming a seed metal covering the part of the metal wiring exposed from the opening, and an inside face and an around portion of the opening of the organic insulating layer, forming a mask covering an edge of the seed metal and exposing part of the seed metal formed in the opening, and forming a barrier metal on the seed metal exposed from the mask by electroless plating. The mask includes an organic material or an inorganic dielectric material.

Abstract: A method includes steps of: acquiring a target wavelength; acquiring a drive condition of a wavelength tunable laser diode; driving the wavelength tunable laser diode based on the drive condition; acquiring a measured value of the first current measured by a first photodetector, a measured value of a second current measured by a second photodetector and a measured value of the drive condition; determining the measured value of the first current as a first target value; calculating a second target value of the second current from the measured value of the drive condition and the target value of the first current; and coinciding a ratio of the measured value of the first current with respect to the measured value of the second current, to a ratio of the first target of the first current with respect to the second target of the second current, by changing the drive condition.

Abstract: A semiconductor device that comprises a substrate with a primary surface and a secondary surface opposite to the primary surface. The primary surface provides a semiconductor active device. The semiconductor device includes a base metal layer deposited on the secondary surface and within the substrate via in which a vacancy is formed, and an additional metal layer on the base metal layer, the additional metal layer having different wettability against a solder as compared to the base metal layer whereby the solder is contactable by the base metal layer and repelled by the additional metal layer. The semiconductor device is die-bonded on the assembly substrate by interposing the solder between the secondary surface and the assembly substrate. The base metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the additional metal layer is in contact with the solder.

Abstract: A semiconductor device including a mounting substrate, a semiconductor chip, a rear-surface metal layer, an AuSn solder layer, and a solder blocking metal layer, is disclosed. The semiconductor chip is mounted on the mounting substrate, and includes front and rear surfaces, and a heat generating element. The rear-surface metal layer includes gold (Au). The AuSn solder layer is located between the mounting substrate and the rear surface to fix the semiconductor chip to the mounting substrate. The solder blocking metal layer is located between the rear surface and the mounting substrate, and in a non-heating region excluding a heating region in which the heat generating element is formed. The solder blocking metal layer includes at least one of NiCr, Ni and Ti and extends to an edge of the semiconductor chip. A void is provided between the solder blocking metal layer and the AuSn solder layer.

Abstract: A process of forming a field effect transistor (FET) of a type of high electron mobility transistor (HEMT) reducing damages caused in a semiconductor layer is disclosed. The process carries out steps of: (a) depositing an insulating film on a semiconductor stack; (b) depositing a conductive film on the insulating film; (c) forming an opening in the conductive film and the insulating film by a dry-etching using ions of reactive gas to expose a surface of the semiconductor stack; and (d) forming a gate electrode to be in contact with the surface of the semiconductor stack through the opening, the gate electrode filling the opening in the conductive film and the insulating film.

Abstract: A semiconductor device is made by: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.

Abstract: A semiconductor module includes a base plate made of a metal, an insulating frame provided on a peripheral edge portion of the base plate, a lead made of a metal and provided on the frame, and a semiconductor device mounted on the base plate in a space surrounded by the frame, wherein the frame is fixed to the base plate by a bonding material containing silver, the frame has concave portions formed in an inner portion which is a corner portion on a space side and an outer portion which is a corner portion on a side opposite to the inner portion in a surface thereof which faces the base plate, and the concave portions are filled with a coating material.

Abstract: A semiconductor device manufacturing method includes: forming an electrode including an Ni layer and an Au layer successively stacked on a semiconductor layer; forming a Ni oxide film by performing heat treatment to the electrode at a temperature of 350° C. or more to deposit Ni at least at a part of a surface of the Au layer and to oxidize the deposited Ni; and forming an insulating film in contact with the Ni oxide film and containing Si.

Abstract: A semiconductor device and a process of forming the semiconductor device are disclosed. The semiconductor device type of a high electron mobility transistor (HEMT) has double SiN films on a semiconductor layer, where the first SiN film is formed by the lower pressure chemical vapor deposition (LPCVD) technique, while, the second SiN film is deposited by the plasma assisted CVD (p-CVD) technique. Moreover, the gate electrode has an arrangement of double metals, one of which contains nickel (Ni) as a Schottky metal, while the other is free from Ni and covers the former metal. A feature of the invention is that the first metal is in contact with the semiconductor layer but apart from the second SiN film.

Abstract: A semiconductor device manufacturing method includes: forming an electrode including an Ni layer and an Au layer successively stacked on a semiconductor layer; forming a Ni oxide film by performing heat treatment to the electrode at a temperature of 350° C. or more to deposit Ni at least at a part of a surface of the Au layer and to oxidize the deposited Ni; and forming an insulating film in contact with the Ni oxide film and containing Si.