Patents Assigned to Sumitomo Electric Device Innovations, Inc.
  • Patent number: 10826622
    Abstract: A wavelength de-multiplexing system that receives a wavelength multiplexed signal and generates electrical signals corresponding to the optical signals is disclosed. The optical receiver module includes a lens, a lens unit, and an optical de-multiplexer (O-DeMux). The lens converts the wavelength multiplexed signal into a quasi-collimated beam. The lens unit narrows a diameter of the quasi-collimated beam. The O-DeMux de-multiplexes the narrowed quasi-collimated beam coming from the lens unit by wavelength selective filters (WSFs) each having optical distances from the lens unit different from each other.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: November 3, 2020
    Assignees: Sumitomo Electric Industries, Ltd., Sumitomo Electric Device Innovations, Inc.
    Inventors: Kazuaki Mii, Hiroshi Hara, Fumihiro Nakajima
  • Publication number: 20200333639
    Abstract: An optical modulator carrier assembly includes a optical modulator, a transmission line substrate, a first via, a second via and a wire having an inductor component provided on a second surface of the transmission line substrate, and electrically connecting between the another end of the first via and the another end of the second via. The one end of the first via, the cathode electrode pad, the terminating resistor, the one end of the second via are arranged on the in this order.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 22, 2020
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Masahiro HIRAYAMA
  • Publication number: 20200328722
    Abstract: A high frequency amplifier 1 includes an input terminal PIN, an output terminal POUT, a transistor 5 configured to amplify an RF signal applied to the input terminal PIN, a matching circuit 9 for a fundamental of the RF signal and a reflection circuit 7 for a harmonic relative to the fundamental, the matching circuit 9 and the reflection circuit 7 being connected in series between the transistor 5 and the output terminal POUT, an extraction circuit 13 configured to extract a harmonic appearing at the output terminal POUT, processing circuits 15, 17 configured to adjust a phase and intensity of the harmonic extracted by the extraction circuit 13, and a multiplexing circuit 19 configured to multiplex the harmonic processed by the processing circuits 15, 17 to the harmonic reflected by the reflection circuit 7 and give the multiplexed harmonic to the transistor 5.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 15, 2020
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Yuji KIMOTO
  • Publication number: 20200328199
    Abstract: A receiver optical module that receives an optical signal and generating an electrical signal corresponding to the optical signal is disclosed. The module includes a photodiode (PD), a sub-mount, a pre-amplifier, and a stem. The sub-mount, which is made of insulating material, mounts the PD thereon. The pre-amplifier, which receives the photocurrent generated by the PD, mounts the PD through the sub-mount with an adhesive. The pre-amplifier generates an electrical signal corresponding to the photocurrent and has signal pads and other pads. The stem, which mounts the pre-amplifier, provides lead terminals wire-bonded with the signal pads of the pre-amplifier. The signal pads make distances against the sub-mount that are greater than distances from the other pads to the sub-mount.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Kyohei MAEKAWA
  • Patent number: 10802303
    Abstract: An optical module including a source assembly is disclosed. The source assembly provides a semiconductor optical device, a wiring substrate, and a bridge substrate. The semiconductor optical device includes an electrode and a pad that receives a driving signal therethrough. The wiring substrate, which is arranged side by side with respect to the semiconductor optical device, provides a signal line and a ground line surrounding the signal line. The bridge substrate includes a signal line and a ground line surrounding the signal line. A feature of the optical module is that the bridge substrate is placed on the semiconductor optical device and the wiring substrate such that a transmission line thereof faces the semiconductor optical device and the wiring substrate, and one end of the signal line thereof is connected with the pad of the semiconductor optical device through a post, and another end of the signal line thereof is connected with an end of the signal line in the wiring substrate through another post.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: October 13, 2020
    Assignees: Sumitomo Electric Device Innovations, Inc., Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Yamaji, Yasushi Fujimura, Taichi Misawa
  • Patent number: 10797653
    Abstract: A consecutive Doherty amplifier is disclosed. The Doherty amplifier includes a carrier amplifier, a power splitter, a peak amplifier, and a phase compensator. The carrier amplifier receives a radio frequency signal with interposing any signal splitters. The power splitter splits an output of the carrier amplifier into first and second split signals. The phase compensator transfers the second split signal to the peak amplifier. The first split signal is combined with the output of the peak amplifier.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 6, 2020
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventors: Andrey Grebennikov, James Wong, Naoki Watanabe
  • Publication number: 20200312982
    Abstract: A process of forming a field effect transistor (FET) of a type of high electron mobility transistor (HEMT) reducing damages caused in a semiconductor layer is disclosed. The process carries out steps of: (a) depositing an insulating film on a semiconductor stack; (b) depositing a conductive film on the insulating film; (c) forming an opening in the conductive film and the insulating film by a dry-etching using ions of reactive gas to expose a surface of the semiconductor stack; and (d) forming a gate electrode to be in contact with the surface of the semiconductor stack through the opening, the gate electrode filling the opening in the conductive film and the insulating film.
    Type: Application
    Filed: April 15, 2020
    Publication date: October 1, 2020
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Tadashi WATANABE, Hajime MATSUDA
  • Patent number: 10790385
    Abstract: A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 29, 2020
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Ken Nakata
  • Publication number: 20200304212
    Abstract: A wavelength de-multiplexing system that receives a wavelength multiplexed signal and generates electrical signals corresponding to the optical signals is disclosed. The optical receiver module includes a lens, a lens unit, and an optical de-multiplexer (O-DeMux). The lens converts the wavelength multiplexed signal into a quasi-collimated beam. The lens unit narrows a diameter of the quasi-collimated beam. The O-DeMux de-multiplexes the narrowed quasi-collimated beam coming from the lens unit by wavelength selective filters (WSFs) each having optical distances from the lens unit different from each other.
    Type: Application
    Filed: June 2, 2020
    Publication date: September 24, 2020
    Applicants: Sumitomo Electric Industries, Ltd., Sumitomo Electric Device Innovations, Inc.
    Inventors: Kazuaki MII, Hiroshi Hara, Fumihiro Nakajima
  • Publication number: 20200294872
    Abstract: A semiconductor package including a metal base, a side wall, and at least one metal lead is disclosed. The metal base has a main surface to mount at least one semiconductor element. The side wall has a frame shape and is disposed on the main surface. The side wall includes a first side wall portion made of a resin and a second side wall portion made of a resin. The second side wall portion is placed on the first side wall portion and joined to the first side wall portion with an adhesive. The metal lead is partially sandwiched between the first side wall portion and the second side wall portion. A first end of the metal lead is exposed inside of the side wall, and a second end of the metal lead is located outside of the side wall.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 17, 2020
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Takashi KITAWADA
  • Publication number: 20200294941
    Abstract: Provided is a microwave integrated circuit including: a semiconductor substrate; a plurality of amplification units that are formed in the semiconductor substrate; a wiring that is formed in one layer wiring excluding an uppermost layer wiring and a lowermost layer wiring among a plurality of layer wirings formed on the semiconductor substrate and is used for supplying power to the plurality of amplification units; and a plurality of vias that connect a plurality of conductive regions formed in the layer wiring with the wiring interposed therebetween and other conductive regions formed in a region interposing the wiring in the two layer wirings immediately above and immediately below the layer wiring, in which each of the plurality of vias forms a via structure connected to the conductive regions of the lowermost layer wiring by a plurality of other vias.
    Type: Application
    Filed: March 11, 2020
    Publication date: September 17, 2020
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Kenshi Naito
  • Publication number: 20200279818
    Abstract: A field effect transistor includes: a semiconductor region including a first inactive region, an active region, and a second inactive region arranged side by side in a first direction; a gate electrode, a source electrode, and a drain electrode on the active region; a gate pad on the first inactive region; a gate guard on and in contact with the semiconductor region, the gate guard being apart from the gate pad and located between an edge on the first inactive region side of the semiconductor region and the gate pad; a drain pad on the second inactive region; a drain guard on and in contact with the semiconductor region, the drain guard being apart from the drain pad and located between an edge on the second inactive region side of the semiconductor region and the drain pad; and a metal film electrically connected to the gate guard.
    Type: Application
    Filed: February 26, 2020
    Publication date: September 3, 2020
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Chihoko AKIYAMA
  • Publication number: 20200279822
    Abstract: There is provided a method for manufacturing a semiconductor device comprising: forming a first organic insulating layer on a semiconductor region; forming a bump base film including an edge portion contacting with the first organic insulating layer; performing heat treatment of the bump base film; and forming a second organic insulating layer so as to cover the edge portion of the bump base film and the first organic insulating layer around the bump base film while contacting with the first organic insulating layer, the second organic insulating layer being provided with a first opening that exposes a surface of the bump base film.
    Type: Application
    Filed: February 25, 2020
    Publication date: September 3, 2020
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Keita MATSUDA
  • Patent number: 10763802
    Abstract: An amplifier module that implements two or more amplifying units connected in series is disclosed. The amplifier module includes a package, input and output terminals, two or more amplifying units including the first unit and the final unit, an output bias terminal for supplying an output bias to one of amplifying units except for the final unit, and an input bias terminal for supplying an input bias to another one of the amplifying units except for the first unit. A feature of the amplifier module is that the output bias terminal and the input bias terminal are disposed in axial symmetry with respect to a reference axis connecting the input terminal with the output terminal in one side of the package.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 1, 2020
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Naoyuki Miyazawa
  • Patent number: 10756507
    Abstract: A process of forming a semiconductor optical device is disclosed. The semiconductor optical device provides a waveguide structure accompanied with a heater for varying a temperature of the waveguide structure. The process includes steps of: (a) forming a striped mask on a semiconductor substrate; (b) selectively growing a dummy layer on the semiconductor substrate; (c) removing the patterned mask; (d) burying the dummy layer by a supplemental layer; (e) exposing a portion of the dummy layer by etching a portion of the supplemental layer; (f) and removing the dummy layer by immersing the dummy layer within a solution that shows an etching rate for the dummy layer enough faster than an etching rate for the supplemental layer and the substrate so as to leave a void in a region the dummy layer had existed.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: August 25, 2020
    Assignees: Sumitomo Electric Industries, Ltd., Sumitomo Electric Device Innovations, Inc.
    Inventors: Toshimitsu Kaneko, Takuya Fujii, Masami Ishiura, Taro Hasegawa, Toshiyuki Taguchi
  • Publication number: 20200266275
    Abstract: Disclosure is a method for manufacturing a semiconductor device. The method includes forming a source electrode and a drain electrode on a nitride semiconductor layer formed on a main surface of a SiC substrate, forming a gate electrode having a laminated structure including a Ni layer and an Au layer on the Ni layer between the source electrode and the drain electrode on the nitride semiconductor layer and forming a first metal film having the same laminated structure as the gate electrode in a region adjacent to the source electrode with an interval therebetween, forming a second metal film to contact with the source electrode and the first metal film, forming a hole being continuous with the first metal film from a back surface of the SiC substrate, and forming a metal via being continuous with the first metal film from the back surface in the hole.
    Type: Application
    Filed: February 14, 2020
    Publication date: August 20, 2020
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Shunsuke KURACHI, Tsutomu Komatani
  • Patent number: 10750621
    Abstract: A process of assembling a semiconductor device is disclosed. The process includes steps of arraying metal bases on a carrier; applying sintered metal paste simultaneously onto the bases; disposing a substrate simultaneously onto the sintered metal paste where the substrate includes side walls corresponding to the bases and a wiring layer common the bases; and volatilizing solvent contained in the sintered metal paste.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: August 18, 2020
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Shingo Inoue
  • Patent number: 10749314
    Abstract: A method of determining initial parameters and target values for tuning an emission wavelength of a wavelength tunable laser capable of emitting laser light in a substantial wavelength range is disclosed. The method iterates an evaluation of initial parameters and target values at target wavelengths in a preset order. The evaluation includes steps of supplying empirically obtained parameters to the t-LD, confirming whether the t-LD generates an optical beams, determining the initial parameters and the target values by carrying out feedback loops of the AFC and the APC when the t-LD generates the optical beam, or shifting the wavelength range so as to exclude the current target wavelength when the t-LD generates no optical beam.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: August 18, 2020
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Hirokazu Tanaka
  • Publication number: 20200258796
    Abstract: A semiconductor module includes a base plate made of a metal, an insulating frame provided on a peripheral edge portion of the base plate, a lead made of a metal and provided on the frame, and a semiconductor device mounted on the base plate in a space surrounded by the frame, wherein the frame is fixed to the base plate by a bonding material containing silver, the frame has concave portions formed in an inner portion which is a corner portion on a space side and an outer portion which is a corner portion on a side opposite to the inner portion in a surface thereof which faces the base plate, and the concave portions are filled with a coating material.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 13, 2020
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC
    Inventor: Tomoki OHNO
  • Patent number: 10741591
    Abstract: A semiconductor integrated optical device includes: a supporting base including semi-insulating semiconductor; a first photoelectric convertor having first photodiode mesas; a second photoelectric convertor having second photodiode mesas; a first 90° optical hybrid having at least one first multimode waveguide mesa; a second 90° optical hybrid having at least one second multimode waveguide mesa; an optical divider mesa; first and second input waveguide mesas coupling the first and second 90° optical hybrids with the optical divider mesa, respectively; a conductive semiconductor region disposed on the supporting base, the conductive semiconductor region mounting the first photodiode mesas, the second photodiode mesas, the first multimode waveguide mesas, the second multimode waveguide mesas, and the optical divider mesa; a first island semiconductor mesa extending between the first and second multimode waveguide mesas; and a first groove extending through the first island semiconductor mesa and the conductive
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 11, 2020
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Hideki Yagi, Naoko Konishi, Koji Ebihara, Takuya Okimoto