Abstract: A method for overflow detection using partial evaluations. The method includes obtaining a section of code from a source code file stored on a storage device, analyzing the section of code to identify a buffer with an index, determining a plurality of statements that are statically-computable and dependent on the index of the buffer, and generating a code segment including the plurality of statements. The method further includes replacing an access statement of the plurality of statements with a conditional statement returning true when bounds of the buffer are exceeded, where the access statement uses the index to access the buffer, adding an unconditional statement returning false to the code segment, and executing the code segment on a computer processor to obtain a determination of whether the bounds of the buffer are exceeded.

Abstract: A system and method for controlling access to a shared storage device in a computing cluster having at least two nodes configured as cluster members provide fencing and quorum features without using the device controller hardware/firmware so fencing can be provided with storage devices that do not support disk reservation operations, such as with non-SCSI compliant disks. A polling thread on each node periodically reads a designated storage space on the shared storage device at a polling interval to determine if its corresponding node registration key is present, and halts the node if the key has been removed. A cluster membership agent removes a corresponding node registration key from the designated storage space of the shared storage device and publishes new membership information indicating that the corresponding node has departed the cluster only after delaying for a time period greater than the polling interval.

Abstract: A method for compiling source code, involving: obtaining a statement of the source code comprising a method call, where the source code is composed in a statically-typed programming language; determining whether the method call is a dynamic method call; upon determining that the method call is a dynamic method call, compiling a dynamic method invocation without performing type checking on the method call; upon determining that the method call is not a dynamic method call: performing type checking on the method call, selecting a target method to invoke, and compiling a static method invocation to invoke the target method.

Abstract: The described embodiments relate to a processor that speculatively executes instructions. During operation, the processor often executes instructions in a speculative-execution mode. Upon detecting an impending pipe-clearing event while executing instructions in the speculative-execution mode, the processor stalls an instruction fetch unit to prevent the instruction fetch unit from fetching instructions. In some embodiments, the processor stalls the instruction fetch unit until a condition that originally caused the processor to operate in the speculative-execution mode is resolved. In alternative embodiments, the processor maintains the stall of the instruction fetch unit until the pipe-clearing event has been completed (i.e., has been handled in the processor).

Abstract: A method for transferring execution to a subsequent operating system. The method includes rebooting a computer system. Rebooting the computer system includes initializing an in-kernel boot loader. The in-kernel boot loader executes in a kernel of an initial operating system. Rebooting the computer system further includes populating, by the in-kernel boot loader, an initialization data structure using system data gathered during the execution of the initial operating system, loading, by the in-kernel boot loader, the subsequent operating system, and transferring control of the computer system from the initial operating system to the subsequent operating system. The subsequent operating system accesses the initialization data structure to identify available hardware. The method further includes executing the subsequent operating system on the available hardware of the computer system.

Abstract: A system for controlling energy usage in a server having a processor, where the system includes a memory for storing energy cost information, and a controller for determining a transaction rate for the processor. The controller is also for determining a cumulative of energy expended by the server based on the determined transaction rate for each of a number of available power level states (P-states) for operation of the processor, and for selecting one of the available P-states for operation of the processor based on the determined cumulative energy expended and the stored energy cost information.

Abstract: A multi-chip module (MCM) is described. This MCM includes multiple sites, where a given site in the multiple sites includes multiple chips with proximity connectors that communicate information through proximity communication within the MCM via multiple components associated with the given site. Note that the MCM includes global redundancy and local redundancy at the given site. In particular, the global redundancy involves providing one or more redundant sites in the multiple sites. Furthermore, the local redundancy involves providing one or more redundant chips in the multiple chips and one or more redundant components in the multiple components.

Abstract: An integrated circuit that includes an optical waveguide to convey an optical signal via an optical mode in an on-chip optical waveguide is described. In this integrated circuit, a cross-sectional area of the optical waveguide may be tapered in proximity to an electro-optic modulator in the integrated circuit, such as a germanium electro-optic modulator or a quantum-well (QW) electro-optic modulator. In particular, the cross-sectional area may be tapered from a first diameter distal from the electro-optic modulator to a second diameter proximate to the electro-optic modulator. This so-called ‘inverse taper’ may increase the spatial extent or size of the optical mode, thereby allowing the optical signal to be optically coupled to or from the electro-optic modulator with low optical loss.

Abstract: A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.

Abstract: A tandem fan system with an airflow-straightening heat exchanger removes heat from an airflow while providing optimal airflow pressure. The tandem fan system includes a first fan assembly and a second fan assembly, wherein each fan assembly has an inlet face and an outlet face, and includes at least one fan configured to propel a flow of air from the inlet face to the outlet face. The tandem fan system also includes a heat exchanger coupled between the first and second fan assemblies, wherein the heat exchanger includes at least one fin array and one or more heat pipes. The fin array and heat pipe combination is configured to draw heat from a flow of air that flows through the heat exchanger, and to straighten the flow of air so that the flow is perpendicular to the inlet face of the second fan assembly.

Abstract: A method for use in a datacenter for load balancing services. A native registry is operated to provide a naming service storing service access information for services active in a network. On a node, an instance of a service is provided, and the native registry is updated with access information for the service. The method includes providing a content switch with a node controller such as on a network device. The method includes obtaining, with the node controller, service configuration information for the service from the native registry that includes the service access information. The node controller activates the service on the network by configuring the content switch based on the obtained service configuration information. The method includes the service node publishing a service definition for the service that includes the service access information and other information such as a service name, an IP address, and a load balancing algorithm.

Abstract: The disclosed embodiments provide a system that determines whether to dynamically replicate data segments on a node in a computing cluster that stores a collection of data segments. During operation, the system identifies a data segment from the collection that is predicted to be frequently accessed by future tasks executing in the cluster. The system then determines a slowdown that would result for the current workload of the node if the data segment were to be replicated to the node. The system also determines a predicted future benefit that would be associated with replicating the data segment to the node. If the predicted slowdown is less than the predicted future benefit, the replication system replicates the data segment to the node.

Abstract: A method for encoding a video frame. The method including obtaining a current frame from a video stream, where the video stream includes a number of frames, determining a first base QP value for the current frame, and sending the first base QP value for the current frame to a decoder. The method also includes obtaining a first macroblock from the current frame, where the first macroblock includes a first image on the current frame, determining a first actual quantization parameter (QP) value for the first macroblock, and determining a first reference block for the first macroblock. The method also includes determining a first predicted QP value for the first macroblock using the first reference block, calculating a first ?QP value for the first macroblock, and sending the first ?QP value, a first prediction mode, and a first reference vector to the decoder.

Abstract: A system for conducting a conference call based on a community document. The system includes a data network, a first conference client device and a second conference client device communicatively coupled to the data network, wherein the first conference client device is associated with a first user of the conference call and the second conference client device is associated with a second user of the conference call, and a conference server device communicatively coupled to the data network.

Abstract: Various embodiments herein include one or more of systems, methods, software, and/or data structures to determine voltage margin for a high-speed serial data link. Advantageously, the margin determination may be made during normal operation of the data link (“mission mode”) such that the performance of the data link is not affected by the voltage margin measurements. That is, the margin measurements may be performed “on line” rather than “off line.” To facilitate the voltage margin measurement, a plurality of digital samples from an analog to digital converter (ADC) may be evaluated to determine the most probable bit values (i.e., digital 1's and 0's) that are represented by the digital samples. Then, a method may be used to remove or compensate for ISI effects from one or more of the digital samples, thereby providing an accurate representation of the voltage margin present in a data link. Subsequently, the voltage margin may be periodically monitored over time to detect degradation of the data link.

Abstract: Redundant run-time type information is removed from a compiled program. The redundant type information may be unneeded and/or duplicate. Unneeded type information is removed by selecting instances of type information from read only data sections of object files. The entire compiled program is searched for instructions that use the instances. The instances that do not correspond to such instructions are removed from the object files. Duplicate type information is removed by selecting instances of type information from read only data sections of object files. The read only data sections of the other object files in the compiled program are then searched for the selected instances. The selected instances that exist in the read only data sections of the other object files are removed. Redundant type information may be removed from individual object files before concatenation into a single binary file and/or from a single binary file after concatenation.

Abstract: A base mechanism for use in a multi-chip module (MCM) is described. This base mechanism includes a substrate having top and bottom surfaces. The bottom surface includes first electrical connectors that convey power, and through-substrate vias (TSVs) between the top and bottom surfaces are electrically coupled to these electrical connectors. Furthermore, a bridge chip is rigidly mechanically coupled to the top surface. This bridge chip includes proximity communication connectors that communicate information via proximity communication with one or more island chips in the MCM. Additionally, spacers are rigidly mechanically coupled to the top surface of the substrate. In conjunction with the bridge chip, the spacers define cavities on the top surface, which include second electrical connectors. These second electrical connectors are electrically coupled to the TSVs, and communicate additional information with and convey power to the one or more island chips.

Abstract: A zipper structure includes a first contiguous full-dense-mesh (FDM) array of a first supply in top metal and a second contiguous FDM array of a second supply in top-1 metal, a third contiguous FDM array of the second supply in top metal and a fourth contiguous FDM array of the first supply in top-1 metal, and a signal line, such that portions of the first contiguous FDM array and the second contiguous FDM array overlap and portions of the third contiguous FDM array and the fourth contiguous FDM array overlap. The Zipper structure facilitates connecting the first contiguous FDM array to the fourth contiguous FDM array by VIAs and a first connector lines and the second contiguous FDM array to the third contiguous FDM array by VIAs and a second connector lines, such that portion of the signal line overlaps with the first connector lines and the second connector lines.

Abstract: A method for performing distributed transactions of a cluster. The method includes, in response to a lock request including a first epoch from a first node, setting a local epoch to a maximum of the first epoch and the local epoch, sending a first lock including the local epoch to the first node, and in response to a conflicting lock request including a second epoch from a second node, setting the local epoch to a maximum of the second epoch and the local epoch, where the conflicting lock request is delayed until after the first lock is released. The method further includes, in response to a reintegration request including a third epoch from the first node, setting the local epoch to a maximum of the third epoch and the local epoch and performing a reintegration based on the reintegration request, where the reintegration is logged using the local epoch.

Abstract: A hardware memory control unit that includes a register block and hardware logic. The register block includes, for a hardware memory segment, an access count register for storing an access count, a low threshold register for storing a low threshold, and a high threshold register for storing a high threshold. The hardware logic includes functionality to increment the access count stored in the access count register for each memory access to the hardware memory segment performed during a predefined duration of time, and, at the end of the predefined duration of time, perform a response action when the access count stored in the access count register is less than the low threshold stored in the low threshold register, and perform a response action when the access count stored in the access count register is greater than the high threshold stored in the high threshold register. A power saving mode of the hardware memory segment is modified based on performing the response action.