Abstract: Implementations of the present invention may involve methods and systems to improve the combined power consumption and thermal response of individual components of a computer system as the components are stressed concurrently during simulation or testing of the system. A group of operating system-level instruction sets for several individual components of the computer system may be designed to stress the components and executed concurrently while power and thermal measurements are taken. The instruction sets may utilize one or more software threads of the computer system or hardware threads such that minimal interference between components occurs as the system is tested. Further, the system components may be partitioned between separate instruction sets. By minimizing the interference between the components while the system is operating, a more accurate power consumption and thermal effect measurements may be taken on the computer system to better approximate the performance of the system.

Abstract: A system including first and second virtualized execution environments and a hypervisor for sending packets between virtualized execution environments. The first virtualized execution environment includes a first VNIC associated with a first hardware address (HA), a first proxy VNIC associated with a second HA, and a virtual switch. A Vswitch table for the virtual switch includes entries associating the first HA with the first VNIC and the second HA with the first proxy VNIC. The second virtualized execution environment includes a second proxy VNIC associated with the first HA. The virtual switch receives a first packet associated with the second HA. The virtual switch sends the first packet to the first proxy VNIC when Vswitch table entry associates the second HA with the first proxy VNIC. The first VNIC proxy sends the first packet from the first virtualized execution environment to the second virtualized execution environment using the hypervisor.

Abstract: A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.

Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features mate with each other. In particular, a positive feature may mate with a given pair of negative features, which includes negative features on each of the substrates. Furthermore, at least one of the negative features in the given pair may include a hard magnetic material, and the positive feature and the other negative feature in the given pair may include a soft magnetic material that provide a flux-return path to the hard magnetic material. In this way, the hard magnetic material may facilitate the remateable mechanical coupling of the substrates.

Abstract: In general, the invention relates to replicating a source file system stored on a first memory by obtaining a first unread entry from a changelog associated with the source file system, querying the source file system using the first unread entry to obtain a current first object file status, a current first object file path, a current first parent directory status, and a current first parent directory path, determining, based on the querying, whether a first object file on the source file system has changed at some time after the execution of the first unread entry, if the first object file has not changed, performing a first action on a target file system, and if the first object file has changed, performing a second action on the target file system.

Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. For example, the positive features on one of the surfaces may include pairs of counterposed micro-springs, and the negative features may include pits or grooves on the other surface. When the substrates are mechanically coupled, a given pair of positive features may provide a force in a plane of the other surface. Furthermore, by compressing the MCM so that the surfaces of the substrates are pushed toward each other, the mechanical coupling may be released.

Abstract: An optical module is described. This optical module includes at least two optical devices that communicate with each other using edge-to-edge optical coupling of an optical signal between optical components in the two optical devices. Note that the edge-to-edge optical coupling may occur without mode converters at edges of either of the optical devices. Furthermore, the edge-to-edge optical coupling may be facilitated by an alignment substrate, which is mechanically coupled to the two optical devices. This alignment substrate aligns the edges of the two optical devices so that they are approximately parallel to each other, and aligns the optical components in the two optical devices.

Abstract: A multi-chip module (MCM) is described. This MCM includes two substrates having facing surfaces. Disposed on a surface of a first of these substrates, there is an optical waveguide, having an eigenmode in the plane of the surface, and an optical coupler, which redirects optical signals to and/or from the optical waveguide and a direction normal to the surface. Furthermore, disposed on a surface of a second of the substrates, which faces the surface of the first substrate, and which overlaps the optical coupler, there is an optoelectronic device. This optoelectronic device, which has an eigenmode in a direction perpendicular to the surface of the second substrate, selectively receives or provides the optical signal to and/or from the optical coupler. For example, the selective receiving or providing may be controlled by selectively applying a potential to the quantum-well device, thereby changing the optical properties of the optoelectronic device.

Abstract: A phase-interpolator circuit is described. In the phase-interpolator circuit, an output signal, having a fundamental frequency and a phase, is generated based on a weighted summation of a first reference signal and a second reference signal, where the first reference signal has the fundamental frequency and a first phase, and the second reference signal has the same fundamental frequency and a second phase. Note that contributions of the first reference signal and the second reference signal, respectively, to the output signal are determined based on associated first and second impedance values in a weighting circuit in the phase-interpolator circuit. For example, a programmable capacitance ratio of two capacitors may be used to interpolate between the first reference signal and the second reference signal.

Abstract: A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit.

Abstract: A multi-chip module (MCM) is described. This MCM includes two substrates, having facing surfaces, which are mechanically coupled. Disposed on a surface of a first of these substrates, there is a negative feature, which is recessed below this surface. A positive feature in the MCM, which includes an assembly material other than a bulk material in the substrates, at least in part mates with the negative feature. For example, the positive feature may be disposed on the surface of the other substrate. Alternatively, prior to assembly of the MCM, the positive feature may be a separate component from the substrates (such as a micro-sphere). Note that the assembly material has a bulk modulus that is less than a bulk modulus of the material in the substrates. Furthermore, at least a portion of the positive feature may have been sacrificed when the mechanical coupling was established.

Abstract: Systems and methods for providing mechanically reinforced plated through-holes (PTH) in PCBs, which advantageously allow improved soldering capabilities and reliability, are described herein. Such systems and methods are achieved by reducing the heat sinking effects of PTHs by providing one or more vias surrounding the PTHs to provide an electrical connection between the PTH and the internal and bottom conductive layers of a PCB. In this regard, the PTHs are spaced apart from at least one of the internal conductive layers (e.g., ground or power layers), so the heat sinking effects are reduced. This feature enables molten solder to substantially fill the entire PTH before freezing, thereby improving the mechanical and electrical connection between an electrical component and the PCB. One or more electrically-nonfunctional lands (or “rib reinforcements”) are provided in internal conductive layers to mechanically support the walls of the PCB.

Abstract: Methods and apparatus are provided for integrated deflection, detection and intrusion. Within a single computer system configured for operating system virtualization (e.g., Solaris, OpenSolaris), multiple security functions execute in logically independent zones or containers, under the control and administration of a global zone. Such functions may illustratively include a demilitarized zone (DMZ) and a honeypot. Management is facilitated because all functions work within a single operating system, which promotes the ability to configure, monitor and control each function. Any given zone can be configured with limited resources, a virtual network interface circuit and/or other features.

Abstract: In at least one embodiment, an apparatus for determining one or more affinity groups in a distributed network is provided. A first distributed computing device is operably coupled to a plurality of clients for enabling electronic interactive activities therebetween. The first distributed computing device is configured to detect at least one network interaction among the plurality of clients. The first distributed computing device is further configured to generate at least one weighted value based on the number of detected network interactions. The first distributed computing device is further configured to establish an affinity group comprising at least one client from the plurality of clients based on the at least one weighted value.

Abstract: Computer system fans having fixed operating states corresponding to discreet operating speeds may be controlled by collecting temperature information upstream or downstream of the fans and commanding the fans to switch between the fixed operating states based on the temperature information at a frequency sufficient to controllably achieve speeds between the discreet operating speeds.

Abstract: A productivity software application in which a user chooses actions, from at least one of a menu bar, a tool bar, or a task pane, runs on a computer. While running the productivity software application, the computer monitors actions chosen by the user. Data is generated that represents a navigation menu. The navigation menu includes a limited set of choices based on previous actions chosen by the user in the productivity software application. The computer outputs the data representing the navigation menu for visual display, and receives input indicative of a user choice from the limited set of choices in the navigation menu.

Abstract: Disclosed are systems and methods for reclaiming posted buffers during a direct memory access (DMA) operation executed by an input/output device (I/O device) in connection with data transfer across a network. During the data transfer, the I/O device may cancel a buffer provided by a device driver thereby relinquishing ownership of the buffer. A condition for the I/O device relinquishing ownership of a buffer may be provided by a distance vector that may be associated with the buffer. The distance vector may specify a maximum allowable distance between the buffer and a buffer that is currently fetched by the I/O device. Alternatively, a condition for the I/O device relinquishing ownership of a buffer may be provided by a timer. The timer may specify a maximum time that the I/O device may maintain ownership of a particular buffer. In other implementations, a mechanism is provided to force the I/O device to relinquish some or all of the buffers that it controls.

Abstract: A system and method of spread-spectrum fan control for an air-cooled system is provided for reducing the vibrational and acoustical noise associated with the air-cooled system. The method includes generating a first control signal that controls a blade-passing frequency of a first cooling fan and a second control signal that controls a blade-passing frequency of a second cooling fan, wherein the first and second control signals may be pulse width modulated (“PWM”) signals. One or more noise generators independently vary duty cycles for the first and second PWM signals within a range around respective first and second blade-passing frequency set points. As a result, the blade-passing frequencies for the first and second cooling fans are independently and randomly modulated within a range around the respective first and second blade-passing frequency set points.

Abstract: Some embodiments of the present invention provide a system that maps an address to an entity, wherein the mapping interleaves addresses between a number of entities. During operation, the system receives an address A from a set of X consecutive addresses, wherein the address A is to be mapped to an entity E in a set of Y entities, and wherein Y need not be a power of two. Next, the system obtains F=floor(log2(Y)) and C=ceiling(log2(Y)). The system then calculates L, which equals the value of the F least-significant bits of A. The system also calculates M, which equals the value of the C most-significant bits of A. Next, the system calculates S=L+M. Finally, if S<Y, the system sets E=S. Otherwise, if S?Y, the system sets E=S?Y.

Abstract: The described embodiments provide a configurable clock circuit. The clock circuit includes a control and enable circuit and a clock distribution circuit. During operation, when a signal on an enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a clock mode, the control and enable circuit generates an enable signal on a control output to enable a signal on a clock input to propagate through the clock distribution circuit to the clock output. Alternatively, when a signal on the enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a pulse mode, the control and enable circuit generates a pulsed control signal on the control output to control a length of a pulse generated from the clock input on a clock output by the clock distribution circuit.