Abstract: A method of optimizing MOSFET device production which includes defining key independent parameters, formulating those key independent parameters into a canonical variational form, calculating theoretical extracted parameters using at least one of key independent parameters in canonical variational form, physics-based analytical models, or corner models. The method also includes calculating simulated characteristics of a device using the key independent parameters and extracting target data parameters based on at least one of measured data and predicted data, comparing the simulated characteristics to the target data parameters, and modifying the theoretical extracted parameters or key independent parameters in canonical form as a result of the comparison. Then, calculating and outputting the simulated characteristics based on the modified theoretical extracted parameters and the modified key independent parameters in canonical form.

Abstract: Some embodiments of the present invention provide a system for operating a store queue, wherein the store queue buffers stores that are waiting to be committed to a memory system in a processor. During operation, the system examines an entry at the head of the store queue. If the entry contains a membar token, the system examines an unacknowledged counter that keeps track of the number of store operations that have been sent from the store queue to the memory system but have not been acknowledged as being committed to the memory system. If the unacknowledged counter is non-zero, the system waits until the unacknowledged counter equals zero, and then removes the membar token from the store queue.

Abstract: A mechanism is disclosed for implementing fast locking in a multi-threaded system. This mechanism enables fast locking to be performed even on an operating system platform that does not allow one thread to assign ownership of a lock on a mutex to another thread. In addition, the mechanism performs locking in a manner that ensures priority correctness and is low-memory safe. In one implementation, the priority correctness is achieved by using operating system mutexes to implement locking, and the low-memory safe aspect is achieved by pre-allocating a memory section to each thread. This pre-allocated memory section ensures that a thread will have sufficient memory to obtain a lock, even when a system is in a low-memory state. With this mechanism, it is possible to implement locking in a safe and efficient manner.

Abstract: A method of writing data to and reading data from a storage medium includes cycle slip detection and correction. An LDPC matrix includes a first area for cycle slip detection and correction. The first area satisfies a set of conditions such that a cycle slip at a particular position creates a pattern of parity check errors indicative of the position and polarity of the cycle slip. Writing user data to the storage medium includes encoding the user data with parity data according to the LDPC matrix. Reading the user data and the parity data from the storage medium includes decoding the user data and the parity data according to the LDPC matrix. Decoding includes, upon detecting a pattern of parity check errors indicative of the position and polarity of a detected cycle slip, correcting the detected cycle slip.

Abstract: A cooling system for cooling computer component with a liquid provided at atmospheric pressure, or low pressure, that flows through channel defined in the computer component. The liquid is pumped from a reservoir to a discharge port, or weir, that is located above the computer component. The liquid flows through an in-feed manifold to diverters that direct the liquid into in-feed tanks located above a row of the computer component. The liquid flows through the channels and flow control orifices to a drain that returns the liquid to the reservoir.

Abstract: A chip package is described. This chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. For example, the ramp component may be electrically coupled to the semiconductor dies using: microsprings, an anisotropic film, and/or solder. Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique. By removing the need for costly and area-consuming through-silicon vias (TSVs) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.

Abstract: One or more embodiments of the present invention relate to a method for duplicate virtual function table removal. The method includes identifying, using a processor of a computer, a first virtual function table formed when a first source code is compiled into a first object code. The method further includes using the processor, identifying a second virtual function table formed when a second source code is compiled into a second object code. The method further includes, independent of linking the first object code to a first executable binary code and the second object code to a second executable binary code, identifying, using the processor, that the first virtual function table and the second virtual function table are identical and, using the processor, deleting the second virtual function table.

Abstract: In at least one embodiment, an apparatus for providing resources from a plurality of on-board device nodes to a hot-plugged device node in a computer is provided. The apparatus comprises a resource manager configured to receive a resource request over a bus system indicative of a set of desired resources from the hot-plugged device node. The resource manager is further configured to probe a parent device and at least one upper level device node positioned above the parent device node for the set of desired resources. The resource manager is further configured to provide the set of desired resources from the parent device node and one or more nodes of the at least one upper level device node over the bus system for transmission to the hot-plugged device node to enable the hot-plugged device node to operate in the intended manner.

Abstract: A method for scheduling a thread on a plurality of processors that includes obtaining a first state of a first processor in the plurality of processors and a second state of a second processor in the plurality of processors, wherein the thread is last executed on the first processor, and wherein the first state of the first processor includes the state of a cache of the first processor, obtaining a first estimated instruction rate to execute the thread on the first processor using an estimated instruction rate function and the first state, obtaining a first estimated global throughput for executing the thread on the first processor using the first estimated instruction rate and the second state, obtaining a second estimated global throughput for executing the thread on the second processor using the second state, comparing the first estimated global throughput with the second estimated global throughput to obtain a comparison result, and executing the thread, based on the comparison result, on one selected fr

Abstract: A method and system for creating and executing tasks within a multithreaded application composed according to the OpenMP application programming interface (API). The method includes generating threads within a parallel region of the application, and setting a counter equal to the quantity of the threads. The method also includes, for each one of the plurality of threads, assigning an implicit task, and executing the implicit task. Further, the method includes, upon encountering a task construct, during execution of the implicit tack, for an explicit asynchronous task generating the explicit asynchronous task, adding the explicit asynchronous task to a first task queue, where the first task queue corresponds to the one of the plurality of threads; and incrementing the counter by one.

Abstract: Some embodiments of the present invention provide a system that acquires a lock in a shared memory multiprocessor system. During operation, the system loads the lock into a cache associated with the thread and then reads a value of the lock. If the value indicates that the lock is currently held by another thread, the system periodically executes an instruction that tests a status of the lock. If the status indicates the lock is valid, the system continues to test the status of the lock. Otherwise, if the status indicates that the lock was invalidated by a store, the system attempts to acquire the lock by executing an atomic operation. On the other hand, if the status indicates that the lock was invalidated by an atomic operation, or that the lock is not present in the cache, the system repeats the loading and reading operations.

Abstract: Some embodiments of the present invention provide a system that provides error detection and correction after a failure of a memory component in a memory system. During operation, the system accesses a block of data from the memory system, wherein the memory system is previously determined to have a specific failed memory component. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including a row checkbit column including row-checkbits for each of the R rows, an inner checkbit column including X<R inner checkbits and R?X data bits, and C?2 data-bit columns containing data bits. Note that each column is stored in a different memory component, and the checkbits are generated from the data bits to provide block-level detection and correction for a failed memory component. Next, the system attempts to correct a column of the block from the failed memory component by using the checkbits and the data bits to produce a corrected column.

Abstract: A distributed resource and service management system includes at least one node and a registry service. The at least one node is configured to execute at least one node controller. The registry service is configured to provide at least one service description via a control interface, and to offer logical resources to the at least one node controller. The at least one node controller is configured to discover the registry service, to initiate on-going communications with the registry service, and to execute at least one of queries, updates and inserts to the registry service to maintain service levels.

Abstract: Some embodiments of the present invention provide a system for packet classification and spreading in a virtualized system. The system can use information in a packet's header to determine a destination system-image in the virtualized system, and a packet-spreading policy for the destination system-image. The system can determine a key using the information in a packet's header. Alternatively, the system can hash the information in the packet's header to obtain an index value. Next, the system can use the key or the index value to perform a lookup in a table which associates keys or index values with system images and/or packet-spreading policies. Once the destination system-image and the packet-spreading policy are determined, the system can deliver the packet to a thread on the destination system-image according to the packet-spreading policy.

Abstract: A heat sink for use with a heat generating component includes a molded cooling block including a molded cooling passage for receiving a cooling medium. The cooling block is configured to be positioned in sufficient heat transfer relationship with respect to the heat generating component so that the cooling medium receives heat from the heat generating component.

Abstract: One embodiment provides a system that analyzes a target electromagnetic signal radiating from a monitored system. During operation, the system monitors the target electromagnetic signal using a set of antennas to obtain a set of received target electromagnetic signals from the monitored system. Next, the system calculates a weighted mean of the received target electromagnetic signals using a first pattern-recognition model. The system then subtracts the received target electromagnetic signals from the weighted mean of the received target electromagnetic signals to obtain a set of noise-reduced signals for the monitored system. Finally, the system assesses the integrity of the monitored system by analyzing the noise-reduced signals using a second pattern-recognition model.

Abstract: A system and method of character input using a virtual keyboard, which may have a reduced number of keys. The virtual keyboard may be displayed on a touch screen and may include a plurality of keys. The virtual keyboard may have a plurality of keys, each key having a number of characters or symbols. Characters associated with a particular key may be selected through a series of related touch screen inputs.

Abstract: The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO.

Abstract: In general, the invention relates to reclaiming transmit descriptors by configuring a media access control (MAC) to execute a first MAC layer thread to reclaim a first number of transmit descriptors (TDs) from a first hardware transmit ring (HTR) using a first reclaim algorithm, where the first reclaim algorithm is associated with a first transmission pattern and a first TDR status. The invention further includes receiving, by a virtual NIC (VNIC) executing within the MAC layer, a first number of packets, forwarding the first number of packets to a device driver on the host associated with the physical NIC, and forwarding the first number of packets from the device driver to the physical NIC using the first number of TDs, where the first plurality of TDs are reclaimed by the first MAC layer thread according to the first reclaim algorithm.

Abstract: A computer readable medium that includes computer readable program code embodied therein. The computer readable medium causes the computer system to receive, by a data link rule enforcer, a packet from a packet source of the packets, and obtain a data link rule applying to a data link. The data link is operatively connected to the packet source, and the data link is associated with a media access control (MAC) address. The computer readable medium further causes the computer system to determine, by the data link rule enforcer, whether the packet complies with the data link rule, and drop, by the data link rule enforcer, the packet when the packet fails to comply with the data link rule.