Patents Assigned to Sun Microsystems, Inc.
  • Publication number: 20110153797
    Abstract: A method for performing distributed transactions of a cluster. The method includes, in response to a lock request including a first epoch from a first node, setting a local epoch to a maximum of the first epoch and the local epoch, sending a first lock including the local epoch to the first node, and in response to a conflicting lock request including a second epoch from a second node, setting the local epoch to a maximum of the second epoch and the local epoch, where the conflicting lock request is delayed until after the first lock is released. The method further includes, in response to a reintegration request including a third epoch from the first node, setting the local epoch to a maximum of the third epoch and the local epoch and performing a reintegration based on the reintegration request, where the reintegration is logged using the local epoch.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 23, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Nikita Yurievich Danilov, Eric Barton
  • Publication number: 20110150077
    Abstract: A method for encoding a video frame. The method including obtaining a current frame from a video stream, where the video stream includes a number of frames, determining a first base QP value for the current frame, and sending the first base QP value for the current frame to a decoder. The method also includes obtaining a first macroblock from the current frame, where the first macroblock includes a first image on the current frame, determining a first actual quantization parameter (QP) value for the first macroblock, and determining a first reference block for the first macroblock. The method also includes determining a first predicted QP value for the first macroblock using the first reference block, calculating a first ?QP value for the first macroblock, and sending the first ?QP value, a first prediction mode, and a first reference vector to the decoder.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Kelly Yoshikazu Kishore, Gerard Marius Xavier Fernando, Michael Allen DeMoney
  • Publication number: 20110147907
    Abstract: A system for proximity communication between semiconductor chips includes a package assembly. The package assembly includes a plurality of bridge circuits made of organic or plastic semiconductor material. A plurality of base chips are assembled to the package assembly. The package assembly positions and aligns the plurality of base chips such that the bridge circuits bridge the base chips and enable proximity communication between the base chips.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventor: Ashok V. Krishnamoorthy
  • Publication number: 20110141868
    Abstract: Disclosed herein are aspects of optical tape technology, tape manufacturing, and tape usage.
    Type: Application
    Filed: December 16, 2009
    Publication date: June 16, 2011
    Applicant: SUN MICROSYSTEMS INC.
    Inventor: Faramarz Mahnad
  • Publication number: 20110141863
    Abstract: Disclosed herein are aspects of optical tape technology, tape manufacturing, and tape usage.
    Type: Application
    Filed: December 16, 2009
    Publication date: June 16, 2011
    Applicant: SUN MICROSYSTEMS INC.
    Inventor: Faramarz Mahnad
  • Publication number: 20110145543
    Abstract: A processing unit executes a vector width instruction in a program and the processing unit obtains and supplies the width of an appropriate vector register that will be used to process variable vector processing instructions. Then, when the processing unit executes variable vector processing instructions in the program, the processing unit processes the variable vector processing instructions using the appropriate vector register with the instructions having the same width as the appropriate vector register. The width that the processing unit obtains may be less than an actual width of the appropriate vector register and may set by the processing unit. In this way, many different vector widths can be supported using a single set of instructions for vector processing. New instructions are not required if vector widths are changed and processing units having vector registers of differing widths do not require different code.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Applicant: Sun Microsystems, Inc.
    Inventor: Peter Carl Damron
  • Publication number: 20110145834
    Abstract: A program is executed utilizing a main hardware thread. During execution, an instruction specifies to execute a portion utilizing a worker hardware thread. If a processor state indicator is set to multi-threaded, the specified portion is executed utilizing the worker hardware thread. However, if the processor state indicator is set to single-threaded, the specified portion is executed utilizing the main hardware thread as a subroutine. The main hardware thread may pass parameter data to the worker hardware thread by copying the parameter data register or memory location for the main hardware thread to an equivalent parameter data register or memory location for the worker hardware thread. Similarly, the worker hardware thread may pass return values to the main hardware thread by copying a return value register or memory location for the worker hardware thread to an equivalent return value register or memory location for the main hardware thread.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 16, 2011
    Applicant: Sun Microsystems, Inc.
    Inventor: Peter Carl Damron
  • Publication number: 20110145815
    Abstract: A device list is created for an operating system and/or a virtualized operating system. A bus node is created for each bus. Interface nodes are created as child nodes of the respective bus and a status indicator indicates whether a device connected to the interface is accessible. A device node is created for the device connected to the interface. Virtualized interface nodes are created as child nodes of the device node for each virtual device included in the device and a status indicator indicates whether the respective virtual device is accessible. Then, devices and/or virtual devices may be added and/or removed utilizing the list. After a device and/or virtualized device has been removed for one operating system and/or virtualized operating system, it may then be added to another. In this way, devices and/or virtualized devices can be virtually hot plugged without physically connecting and/or disconnecting devices.
    Type: Application
    Filed: December 11, 2009
    Publication date: June 16, 2011
    Applicant: Sun Microsystems, Inc.
    Inventors: Yong Colin Zou, Wesley Shao, Govinda Tatti, Scott Michael Carter
  • Publication number: 20110141630
    Abstract: Some embodiments of the present invention provide a system that facilitates the operation of a supercapacitor. During operation, the system measures an electrical parameter of the supercapacitor using a set of conductor rings surrounding a capacitor seal of the supercapacitor. Next, the system determines the presence of a leak in the supercapacitor based on the electrical parameter. Finally, the system manages the operation of the supercapacitor based on the presence of the leak.
    Type: Application
    Filed: December 14, 2009
    Publication date: June 16, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Thomas J. Pelc, Jorge E. Martinez-Vargas, JR.
  • Publication number: 20110138149
    Abstract: One embodiment provides a system that prevents duplicate entries in a non-blocking TLB that supports multiple page sizes and speculative execution. During operation, after a request for translation of a virtual address misses in the non-blocking TLB, the system receives a TLB fill. Next, the system determines a page size associated with the TLB fill, and uses this page size to determine a set of bits in the virtual address that identify the virtual page associated with the TLB fill. The system then compares this set of bits with the corresponding bits of other virtual addresses associated with pending translation requests. If the system detects that a second virtual address for another pending translation request is also satisfied by the TLB fill, the system invalidates the duplicate translation request associated with the second virtual address.
    Type: Application
    Filed: December 9, 2009
    Publication date: June 9, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Martin R. Karlsson, Jian-Ming Chang
  • Publication number: 20110135320
    Abstract: A technique for calibrating an optical receiver is described. During this technique, a front-end circuit in the optical receiver receives an optical signal that corresponds to a sequence with alternating groups of symbol types that correspond to binary values, where durations of the groups of a given symbol type, which can correspond to a first binary value or a second binary value, progressively decrease during the sequence. Then, the output of the feedback circuit is adjusted based at least on the sequence. When the durations of groups corresponding to the first binary value and the second binary value reach their minimum values in the sequence, a calibration value corresponding to the output of the feedback circuit is stored for use during a normal operating mode of the optical receiver.
    Type: Application
    Filed: December 9, 2009
    Publication date: June 9, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Philip Amberg, Dinesh D. Patil, Frankie Y. Liu
  • Publication number: 20110138372
    Abstract: The present disclosure provides a compiler prespill phase that reduces or eliminates excessive register pressure, or locations in the code of a program where live virtual registers exceeds physical registers of a target computing device, prior to register allocation. The prespill phase identifies points of excessive register pressure, selects candidate virtual registers, chooses virtual registers to prespill from the candidates, and inserts spill and reload instructions to prespill the chosen registers. The prespill phase may reduce the register pressure such that the live virtual registers only exceed the physical registers by a particular number, the live virtual registers equal the physical registers, or the physical registers exceed the live virtual registers by a particular number. The compiler may then perform one or more early and/or late instruction scheduling phases, including global and/or local instruction scheduling, to optimize the placement of the spill and reload instructions.
    Type: Application
    Filed: December 4, 2009
    Publication date: June 9, 2011
    Applicant: Sun Microsystems, Inc.
    Inventor: Peter Carl Damron
  • Publication number: 20110134915
    Abstract: Methods and apparatus are provided for managing classification of packets within a multi-function input/output device, and for allowing the device's classification tables to be cleared in a non-blocking manner. The input/output device conveys multiple communication connections corresponding to multiple physical and/or virtual PCIe (Peripheral Component Interconnect Express) functions bound to software images executing on hosts. The device comprises gate logic configured to indicate statuses of the functions or the DMA engines bound to the functions. When the gate logic indicates a particular destination function is valid, the packet is transferred normally after being classified. A portion of the logic corresponding to a given function is reprogrammed to indicate the function is invalid when that function is reinitialized (e.g., FLR or Function Level Reset). The function's entries in packet classification tables are cleared afterward.
    Type: Application
    Filed: December 9, 2009
    Publication date: June 9, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventor: Arvind Srinivasan
  • Publication number: 20110135315
    Abstract: An optical receiver is described. This optical receiver includes a digital feedback circuit that biases a front-end circuit, which receives an optical signal, so that an analog electrical signal output by the front-end circuit is calibrated relative to a reference voltage corresponding to a decision threshold of a digital slicer in the optical receiver. In particular, during a calibration mode the feedback circuit may determine and store a calibration value that calibrates the analog electrical signal relative to the reference voltage. Then, during a normal operating mode, the feedback circuit may output a current corresponding to the stored calibration value that specifies a bias point of the front-end circuit.
    Type: Application
    Filed: December 9, 2009
    Publication date: June 9, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Frankie Y. Liu, Dinesh D. Patil, Ronald Ho, Elad Alon
  • Publication number: 20110119528
    Abstract: The described embodiments provide a processor (e.g., processor 102) for executing instructions. During execution, the processor starts by transactionally executing instructions from a protected section of program code. The processor then encounters a transactional failure condition while transactionally executing the instructions from the protected section of program code. In response to encountering the transactional failure condition, the processor enters a transactional-scout mode and speculatively executes subsequent instructions in the transactional-scout mode.
    Type: Application
    Filed: November 13, 2009
    Publication date: May 19, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Martin R. Karlsson, Sherman H. Yip, Shailender Chaudhry
  • Publication number: 20110119318
    Abstract: A method for performing garbage collection promotion, comprising determining that an age of a large young object is greater than a predetermined tenuring threshold, wherein the predetermined tenuring threshold specifies an age beyond which objects are promoted, setting a plurality of types of a plurality of large memory regions from young to old to promote the large young object to a large old object, wherein the plurality of large memory regions host the large young object, scavenging references of the large old object, wherein the large old object is a large promoted object, scanning a large young object list to identify a plurality of unvisited large young objects, wherein a plurality of visited bits of the plurality of unvisited large young objects are unset, and releasing a plurality of unvisited large memory regions, wherein the unvisited large memory regions host the plurality of unvisited large young objects.
    Type: Application
    Filed: November 18, 2009
    Publication date: May 19, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Laurent Phillipe Daynes, Thomas Schatzl
  • Publication number: 20110109356
    Abstract: A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.
    Type: Application
    Filed: November 6, 2009
    Publication date: May 12, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Tamer M. Ali, Robert J. Drost, Chih-Kong Ken Yang
  • Publication number: 20110107050
    Abstract: Methods and apparatus are provided for adaptively triggering garbage collection. During relatively steady or decreasing rates of allocation of free memory, a threshold for triggering garbage collection is dynamically and adaptively determined on the basis of memory drops (i.e., decreases in free memory) during garbage collection. If a significant increase in the rate of allocation of memory is observed (e.g., two consecutive measurements that exceed a mean rate plus two standard deviations), the threshold is modified based on a memory drop previously observed in conjunction with the current memory allocation rate, or a memory drop estimated to be possible for the current allocation rate.
    Type: Application
    Filed: November 5, 2009
    Publication date: May 5, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventor: David Vengerov
  • Publication number: 20110101833
    Abstract: A storage rack for supporting a server chassis in a storage cabinet. The storage rack includes front and rear vertical support members and one or more rack mount kits for slidably supporting one or more computing devices (e.g., servers). Each rack mount kit may include a pair of rail assemblies, each rail assembly including outer, middle and inner rail assemblies. The outer rail assembly may include first and second outer rail members that are slidable relative to each other and one or more locking mechanisms that may be operable to selectively limit sliding or translation of the first and second outer rail members relative to each other. In one arrangement, a locking mechanism may include a ratchet assembly that may allow the first and second outer rail members to slide in a first direction when the locking mechanism is engaged and in the first direction and an opposite second direction when the locking mechanism is released.
    Type: Application
    Filed: October 30, 2009
    Publication date: May 5, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Timothy W. Olesiewicz, Brett C. Ong
  • Publication number: 20110107289
    Abstract: A method and system of merging gated-clock domains in a semiconductor design includes producing, for each subset of clock gating functions in an initial set of clock gating functions, a set of quantified functions produced by existentially quantifying each clock gating function in the subset over a set of variables that are not part of the support sets of the other clock gating functions of the subset. If the set of quantified functions are equal, selecting one as a super clock gating function and adding it to the set of super clock gating functions. The set of super clock gating functions are sorted according to a criterion and the best is selected and added to the set of final clock gating functions. The remaining super clock gating functions are modified to prevent flip-flops gated by the selected super clock gating function from being gated by remaining super clock gating functions.
    Type: Application
    Filed: October 30, 2009
    Publication date: May 5, 2011
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Aravind Oommen, Hemanga Das, Krishnan Sundaresan