Abstract: A fan module for use with fan trays or decks within a computer chassis for forced-air cooling with counter-rotating flow to provide higher static pressure. The fan module may have a conventional side-by-side form factor with a first and second fans supported within first and second housings. The first and second housings are spaced apart and arranged side-by-side. The first fan has a clockwise-rotating blade, and the second fan has a counterclockwise-rotating blade. In the fan module, the first and second fans may be axial fans with the blades rotating about first and second axes that are offset and parallel. In some embodiments, the fan module may have airflow through the first fan in a first direction along the first axis and airflow through the second fan in a second direction along the second axis, with the first and second directions generally matching.

Abstract: A tape drive for reading both new technology tapes and legacy tapes. The tape drive includes a three bump head with two outer read bumps and an inner write bump. The outer read bumps include readers for reading data from tracks of a first width on a first storage tape while the inner write bump includes writers for writing data in tracks of the first storage tape. Legacy readers are provided in the head to read data from tracks of a second width that is greater than the first track width on a second storage tape. The legacy readers are provided by piggybacking or merged-pole techniques in the inner write bump or are provided in one or both of the outer read bumps. The tape drive includes control circuitry with channels for processing data signals from the narrower readers and channels for processing data signals from the wider legacy readers.

Abstract: A method for optimizing executable code includes identifying a plurality of instructions in the executable code matching a predetermined instruction pattern, assessing whether the binary number conforms to a predetermined bit pattern, and transforming the plurality of instructions into transformed instructions when the binary number conforms to the bit pattern.

Abstract: A method and apparatus for performing on-chip voltage sampling of a weakly-driven node of a semiconductor device are disclosed. In some embodiments, the node is a floating node or is capacitively-driven. In some embodiments, it is involved in proximity-based communication. Sampling the node may include isolating the signal to be sampled using a source-follower amplifier before passing it to the sampling circuit. Sampling the node may include biasing the node to a desired voltage using a leaky transistor or other biasing circuit. In some embodiments, the biasing circuit may also be used to calibrate the sampler by coupling one or more calibration voltages to the node in place of a biasing voltage and measuring the sampler output. The sampler may be suitable for sub-sampling high frequency signals to produce a time-expanded, lower frequency version of the signals. The output of the sampler may be a current communicated off-chip for testing.

Abstract: A method for providing a secure lockout from executing application programs is provided. An opaque graphical component obscures graphical components for all executing software (applications) programs on a display apparatus and prevents events from reaching the executing application programs.

Abstract: In computer systems including memory which execute programs of instructions, vtables associated with objects contain pointers which invoke operations to be performed by the program which are related to the objects. The operation invoked may include the step of modifying the pointer such that upon a subsequent reference to the vtable a different operation is invoked.

Abstract: A system that caches a file within a computer system. During operation, the system monitors accesses to the file, wherein the file is located on a storage device. Next, the system analyzes the monitored accesses to determine an access pattern for the file. The system then uses the determined access pattern to adjust a caching policy for the file.

Abstract: A system that includes a network interface for receiving a packets from a network, a classifier operatively connected to the network interface that analyzes each of the packets and determines to which temporary data structure to forward each of packets, wherein the classifier analyzes each packet to determine with which of a plurality of protocols the packet is associated with. Each temporary data structure within the system is configured to receive packets from the classifier, wherein each of the temporary data structures is associated with at least one virtual serialization queue and wherein each of the temporary data structures is configured to store packets associated with at least one of the plurality of protocols. The at least one virtual serialization queue is configured to queue packets from the one of the temporary data structures associated with the at least one virtual serialization queue.

Abstract: A method and mechanism for controlling threads in a multithreaded multicore processor. A processor includes multiple cores, each of which are capable of executing multiple threads. A control register which is shared by each of the cores is utilized to control the status of the threads in the processing system. In one embodiment, the shared register includes a single bit for each thread in the processor. Depending upon the value written to a bit of the shared register, one of three results may occur with respect to a thread which corresponds to the bit. In one embodiment, writing a “0” to a bit of the shared register will cause a corresponding thread to be Parked. Writing a “1” to a bit of the shared register will cause a corresponding thread to either be UnParked or be Reset. Whether writing a “1” to a bit of the register causes the corresponding thread to be UnParked or Reset depends upon a state of the processor.

Abstract: Embodiments of the present invention implement virtual transactional memory using cache line marking. The system starts by executing a starvation-avoiding transaction for a thread. While executing the starvation-avoiding transaction, the system places starvation-avoiding load-marks on cache lines which are loaded from and places starvation-avoiding store-marks on cache lines which are stored to. Next, while swapping a page out of a memory and to a disk during the starvation-avoiding transaction, the system determines if one or more cache lines in the page have a starvation-avoiding load-mark or a starvation-avoiding store-mark. If so, upon swapping the page into the memory from the disk, the system places a starvation-avoiding load-mark on each cache line that had a starvation-avoiding load-mark and places a starvation-avoiding store-mark on each cache line that had a starvation-avoiding store-mark.

Abstract: A system for cooling a semiconductor device is disclosed. The system includes a lid encasing the semiconductor device, a first plurality of carbon nanotubes disposed within the lid, and a fluid system configured to pass a fluid through the lid. Furthermore, a second system for cooling a semiconductor device is disclosed. The second system includes a lid, a first plurality of carbon nanotubes disposed within the lid, and a fluid system configured to pass a fluid through the lid. The lid is configured to be mounted over and encase the semiconductor device. Additionally, a method for cooling a semiconductor device is disclosed. The method includes disposing a first plurality of carbon nanotubes within a lid, mounting the lid over the semiconductor device, and passing a fluid through the lid.

Abstract: In some circumstances a generational garbage collector may be made more efficient by “pre-tenuring” objects or directly allocating new objects in an old generation instead of allocating them in the normal fashion in a young generation. A pre-tenuring decision is made by a two step process. In the first step, during a young-generation collection, an execution frequency is determined for each allocation site and sites with the highest execution frequency are selected as candidate sites. In the second step, during a subsequent young-generation collection, the survival rates are determined for the candidate sites. After this, objects allocated from sites with sufficiently high survival rates are allocated directly in the old generation.

Abstract: A plurality of PCIe switch complexes are interposed between a plurality of I/O devices and a plurality of microprocessor complexes. Each PCIe switching complex comprises a plurality of PCIe switches wherein each switch possesses at least one non-transparent port. The non-transparent port is used to cross-couple each PCIe switch creating an active matrix of paths between the HBAs associated with each I/O device and each microprocessor. The paths between each HBA (I/O device) and each microprocessor are mapped using a recursive algorithm providing each I/O device with direct memory access to each microprocessor.

Abstract: A method for associating sounds with different keypresses, involving receiving an input of a first keypress from a keyboard including a plurality of keys, wherein the keyboard is associated with a computing device, determining whether a key corresponding to the first keypress is one of a plurality of significant elements, wherein the plurality of significant elements is a subset of the plurality of keys, determining a first sound event associated with the key, when the key is one of the plurality of significant elements, and outputting a first sound associated with the first sound event.

Abstract: One particular implementation takes the form of an apparatus or method for parallelizing a sequential power simulation of an integrated circuit device. The implementation may temporally divide the simulation so that separate time segments of the simulation can be run at the same time, thereby reducing he required time necessary to perform the power simulation. More particularly, a logic simulation may be performed on the integrated circuit and snapshots of the logic devices of the integrated circuit may be taken at a specified period. The separate time segments of the simulation may then be simulated in a parallel manner to simulate power consumption of the integrated circuit. Performing the power simulation on the separate time segments may reduce the required time of a typical power consumption simulation of an integrated circuit.

Abstract: Methods and apparatuses are presented for controlling a fully buffered dual inline memory module. In one embodiment, the memory module may include at least two memory chips, a buffer coupled to the at least two memory chips (the buffer serially receiving data to be stored in the at least two memory chips), and a heat sink thermally coupled to the at least two memory chips and thermally coupled to the buffer such that heat generated by the buffer is coupled to a first memory chip within the at least two memory chips. The may be configured such that it operates at a higher temperature than the first memory chip and the refresh rate of the first memory chip may be adjusted when the temperature of the first memory chip is outside of a predetermined range.

Abstract: A plurality of processor cores on a chip is operated in a normal fashion in a debug and diagnostic mode of operation of the processor. A crossbar switch on the chip couples and decouples the plurality of processors to a plurality of banks in a level-two (L2) cache that is also on the chip. As data is passed from each of the processor cores through the crossbar switch to the L2 cache, the data in cached in a first plurality of banks of the L2 cache. The commands associated with the data and information concerning the status of the data in the level-one cache are logged in another plurality of banks of the L2 cache. This logged information can be readout and used in diagnosis and debugging of L1 and L2 cache problems.

Abstract: An elastic power header device and methods of operation are provided to improve both the read and the write margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin, write margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin and the write margin can be more conveniently controlled.

Abstract: A SRAM memory with a read assist circuit is presented. The read assist circuit uses bitline voltage level switches, which are connected to a low power supply and a high power supply. The bitline voltage level switches have a write operation state, a read operation state, and a standby operation state. The write operation state selectively provides the high power supply to bitlines in columns selected for a write operation, and provides the low power supply to bitlines in the remaining columns. The read operation state selectively provides the low power supply to bitlines in columns selected for the read operation, and provides the low power supply to bitlines in the other columns. The standby operation state selectively provides the low power supply to bitlines in all columns when not in the read operation state or the write operation state.

Abstract: A system and method for synchronizing mirrored and striped disk writes. A data storage system may include a client computer system coupled to a first data storage device and a second data storage device and configured to transmit a first data write request. The first storage device may be configured to transmit a sequence number to the client computer system in response to receiving the first data write request. The client computer system may be further configured to transmit a second data write request including the sequence number to the second storage device. The second data storage device may include a counter and is configured to compare a current counter value to the sequence number. If the counter value is equal to the sequence number, the second storage device stores the data bytes corresponding to the second data write request and increments its counter.