Patents Assigned to Sun Microsystems, Inc.
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Patent number: 7684267Abstract: An apparatus for redundancy of a memory array includes a primary memory array including a plurality of memory cells, one or more of which are defective. A redundant array includes a CAM array that includes a plurality of memory cells. The CAM array is addressed by the address of a defective memory location within the primary memory array and provides a match identification and a resource identification. The redundant array also includes a translation array wherein an offset to configure an input/output multiplexer is stored. The redundant array also includes a redundant data array including a plurality of memory cells wherein one or more memory cells of the redundant data array are used instead of one or more defective memory cells of the primary array.Type: GrantFiled: June 18, 2008Date of Patent: March 23, 2010Assignee: Sun Microsystems, Inc.Inventors: Ioannis Orginos, Mamun Rashid, Mark E. Steigerwald
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Patent number: 7685575Abstract: A method for analyzing an application involving obtaining a thread dump of a plurality of threads executing the application, analyzing the thread dump to obtain a result using an aggregation mechanism, and determining a potential error location in source code of the application using the result.Type: GrantFiled: June 8, 2004Date of Patent: March 23, 2010Assignee: Sun Microsystems, Inc.Inventor: Hussein M. Fareed
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Publication number: 20100070933Abstract: A system and method for selectively replacing standard threshold voltage devices with low threshold voltage devices in a digital logic design. The system identifies at least one path having a first timing value, the path having a plurality of standard threshold devices. The path is reverse traversed, or otherwise analyzed or traversed, to identify at least one of the standard threshold devices to possibly replace with a corresponding low threshold device. The system also determines a timing value for the path associated with replacing the at least one standard threshold device with the corresponding low threshold device. Depending the analysis, the standard threshold device may be replaced with a low threshold device, such as when the path timing improves by replacement. Such replacement may be used in various paths, such as paths considered critical paths in a digital logic design.Type: ApplicationFiled: September 18, 2008Publication date: March 18, 2010Applicant: Sun Microsystems, Inc.Inventor: Le Tu Quach
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Patent number: 7680986Abstract: Many conventional lock-free data structures exploit techniques that are possible only because state-of-the-art 64-bit processors are still running 32-bit operating systems and applications. As software catches up to hardware, “64-bit-clean” lock-free data structures, which cannot use such techniques, are needed. We present several 64-bit-clean lock-free implementations: including load-linked/store conditional variables of arbitrary size, a FIFO queue, and a freelist. In addition to being portable to 64-bit software (or more generally full-architectural-width pointer operations), our implementations also improve on existing techniques in that they are (or can be) space-adaptive and do not require a priori knowledge of the number of threads that will access them.Type: GrantFiled: December 30, 2004Date of Patent: March 16, 2010Assignee: Sun Microsystems, Inc.Inventors: Mark S. Moir, Simon Doherty, Victor M. Luchangco, Maurice P. Herlihy
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Patent number: 7679978Abstract: A novel scheme for screening weak memory cell includes a cell coupled to a leakage stress delivery circuitry (LSDC), which, in turn, is coupled to an induced leakage adjustment control (ILAC). The LSDC includes a combination of PMOS transistors, NMOS transistors or both PMOS and NMOS transistors that are controlled by a plurality of stress inducing signals. The PMOS and/or NMOS transistors of the LSDC are coupled to a pair of complementary data lines. The complementary data lines are inputs to a sense amplifier and are outputs of a write driver. The ILAC controls the quantity of the leakage stress applied through the LSDC to the pair of complementary data lines. The ILAC further includes a leakage varying circuitry that is configured to adjust the leakage stress applied to the complementary data lines through the LSDC.Type: GrantFiled: July 11, 2007Date of Patent: March 16, 2010Assignee: Sun Microsystems, Inc.Inventors: Hua-Yu Su, Raymond A Heald, Wen-Jay Hsu, Paul J. Dickinson, Venkatesh P Gopinath, Lik T Cheng, Shih-Huey Wu
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Patent number: 7681019Abstract: Reference architecture instructions are translated into target architecture operations. In some embodiments, an execution unit of a processor executes a function determined from a collection of operations, the function specifying functionality based on instructions, the collection selected from operations translated from the instructions. In further embodiments, the function is specified as a fused operation. Sequences of operations are optimized by fusing collections of operations; fused operations specify a same observable function as respective collections, but advantageously enable more efficient processing. In some embodiments, a collection comprises multiple register operations. Sequences of operations, in a predicted execution order in some embodiments, form traces. In some embodiments, fusing operations requires setting only final architectural state, such as final flag state; intermediate architectural state is used implicitly in a fused operation.Type: GrantFiled: November 17, 2006Date of Patent: March 16, 2010Assignee: Sun Microsystems, Inc.Inventor: John Gregory Favor
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Patent number: 7679948Abstract: A memory circuit for reading and writing data into a SRAM memory array using charge recycling is presented. The write and read circuit includes a cell voltage level switch, a recycle charge storage, a precharge switch, a write enable switch, and column decoder. The cell voltage level switch is connected to a low power supply and a high power supply and has two states of operation: a write operation state and a read operation state. For each state of operation, the voltage level switch selectively provides a power supply if a column has been selected or if the operation is a read or write. The recycle charge storage stores excess charge from SRAM cells after a read operation or after a write operation in unselected columns. After the read or write operation, the recycle charge storage discharges excess charge to the bitlines during bitline precharging.Type: GrantFiled: June 5, 2008Date of Patent: March 16, 2010Assignee: Sun Microsystems, Inc.Inventors: Heechoul Park, Song Kim, Lancelot Kwong
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Patent number: 7681197Abstract: A method of managing nested monitor locks in a computer program is provided for an application having at least a first thread and a second thread wherein a non-synchronized procedure is processed by the application. The first thread executes an outer software module while the second thread executes an inner software module. A processing state of the second thread code is preserved before the second thread is configured to release an outer monitor of the outer software module. The first thread acquires the outer monitor of the outer software module so that actions may be completed. Upon completion of actions by the first thread, the outer monitor of the outer software module is released. The processing state of the second thread is restored, such that, actions of the second thread are allowed to be completed.Type: GrantFiled: November 30, 2005Date of Patent: March 16, 2010Assignee: Sun Microsystems, Inc.Inventor: Karen Kinnear
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Patent number: 7680142Abstract: A communications chip having a plurality of ports. Each port is provided with an interface for attachment to an external communications facility to exchange data traffic. There is also a switching matrix for routing data traffic on the chip between the ports. The chip further includes a plurality of logic analyzers. Each logic analyzer is associated with a corresponding one of the ports. Each logic analyzers is operable to monitor data traffic passing through its corresponding port and to trigger on one or more predetermined conditions relating to the monitored data traffic. The chip further includes a control interface to allow reconfiguration of the predetermined conditions for at least one of the logic analyzers.Type: GrantFiled: May 11, 2004Date of Patent: March 16, 2010Assignee: Sun Microsystems, Inc.Inventors: Knut Tvete, Hans Rygh, Bjorn Dag Johnsen
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Patent number: 7681247Abstract: A semiconductor device includes a stored device identifier that is accessible to external systems, and a stored secret key that is inaccessible to external systems. The device also includes an input, which in operation receives a system identifier, representing the system into which the device is to be incorporated, and an authorization key. An authorization unit within the device is then used for enabling or disabling the device in accordance with the values of the stored secret key, the received system identifier and the authorization key. The authorization key is typically supplied by a support center in response to being notified of the device identifier. In one embodiment, the authorization unit encrypts the system identifier using the stored secret key as the encryption key and then compares the result against the authorization key.Type: GrantFiled: February 27, 2003Date of Patent: March 16, 2010Assignee: Sun Microsystems, Inc.Inventor: Emrys J. Williams
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Patent number: 7678984Abstract: Method and apparatus for programmatically generating interesting audio file playlists. A playlist generation mechanism may use an N-gram model of audio file ordering patterns found in a collection of human-generated playlists to automatically generate new playlists. Given play histories indicating one or more played audio files as input, statistical methods may be used to look for sequences of audio files that occur a statistically significant number of times in the N-gram model for inclusion in new, interesting playlists that incorporate the human element found in the collection of playlists. In some embodiments, one more backoff probability methods may be used to provide additional candidate audio files for playlists if there is insufficient coverage for an audio file in the N-gram model. In one embodiment, a class-based statistical model incorporating higher-level statistics for the audio files may be used to weight selection of audio file transitions from the N-gram model.Type: GrantFiled: October 13, 2005Date of Patent: March 16, 2010Assignee: Sun Microsystems, Inc.Inventor: Paul B. Lamere
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Patent number: 7679518Abstract: A meeting facilitation tool may perform and/or facilitate the planning, scheduling, holding, and/or following up of meeting related activities. A meeting facilitation tool may schedule a meeting time by interacting with meeting participants to determine a time range during which all the participants are available. Additionally, a meeting facilitation tool may programmatically interact with calendar data to schedule the meeting with each participant. A meeting facilitation tool may also allow reviewing of information for previous meetings. Additionally, a meeting facilitation tool may configure and/or initiate teleconferencing or video conferencing as well as the audio and/or video recording of the meeting. A meeting facilitation tool may also track and completion of action items assigned during a meeting.Type: GrantFiled: June 28, 2005Date of Patent: March 16, 2010Assignee: Sun Microsystems, Inc.Inventors: Kuldipsingh A. Pabla, Eric Pouyoul, Calvin J. Cheng
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Patent number: 7680989Abstract: We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms and define aspects of an instruction set architecture consistent therewith.Type: GrantFiled: August 17, 2006Date of Patent: March 16, 2010Assignee: Sun Microsystems, Inc.Inventors: Mark S. Moir, Robert E. Cypher, Paul N. Loewenstein
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Patent number: 7680624Abstract: One embodiment of the present invention provides a system that performs a real-time root-cause-analysis for a degradation event associated with a component under test. During operation, the system monitors a telemetry signal collected from the component, and while doing so, attempts to detect an anomaly in the telemetry signal. If an anomaly is detected in the telemetry signal, the system performs a failure analysis on the telemetry signal in real-time while the telemetry signal is degrading. Next, the system identifies a failure mechanism for the component based on the failure analysis.Type: GrantFiled: April 16, 2007Date of Patent: March 16, 2010Assignee: Sun Microsystems, Inc.Inventors: David K. McElfresh, Dan Vacar, Kenny C. Gross, Leoncio D. Lopez
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Patent number: 7681188Abstract: One embodiment of the present invention provides a system that facilitates locked prefetch scheduling in general cyclic regions of a computer program. The system operates by first receiving a source code for the computer program and compiling the source code into intermediate code. The system then performs a trace detection on the intermediate code. Next, the system inserts prefetch instructions and corresponding locks into the intermediate code. Finally, the system generates executable code from the intermediate code, wherein a lock for a given prefetch instruction prevents subsequent prefetches from being issued until the data value returns for the given prefetch instruction.Type: GrantFiled: April 29, 2005Date of Patent: March 16, 2010Assignee: Sun Microsystems, Inc.Inventors: Partha P. Tirumalai, Spiros Kalogeropulos, Yonghong Song
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Publication number: 20100059201Abstract: A liquid cooled rack with compliant heat exchanger support structure includes a rack having a rigid frame for supporting electronic components therein, a plurality of flexible supports connected to the rigid frame, and a liquid-fed heat exchanger mounted within the rack via the plurality of flexible supports. The plurality of flexible supports are connected to the heat exchanger and configured to flexibly support the liquid-fed heat exchanger with respect to the rigid frame.Type: ApplicationFiled: September 11, 2008Publication date: March 11, 2010Applicant: Sun Microsystems, Inc.Inventors: Andrew R. Masto, Marlin R. Vogel, David W. Copeland
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Patent number: 7676561Abstract: Determining server capabilities during a discrete time period, or interval, allows for more efficient processing of client requests. Updating a proportional server capability load balancing information encoding at intervals allows a load balancer to handle client requests without the overhead of determining current server capabilities. Decision-making can be reduced to quick selection of one of a group of servers without considering the server's capability, since the server's capability has previously been considered when collecting the load balancing information.Type: GrantFiled: December 2, 2003Date of Patent: March 9, 2010Assignee: Sun Microsystems, Inc.Inventors: Shirish Rai, Christine Tomlinson
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Patent number: 7676475Abstract: A method for gathering management information about an asset that includes receiving a first request for the management information about the asset, wherein the first request complies with the information model format, identifying a data acquisition (DAQ) definition for the DAQ definition complies with the DAQ format, triggering a protocol handler according to the DAQ definition, receiving the management information from the protocol handler about the asset, and updating a cache entry with the management information.Type: GrantFiled: June 22, 2006Date of Patent: March 9, 2010Assignee: Sun Microsystems, Inc.Inventors: Arieh Markel, Alexander G. Vul, Brandon Eugene Taylor, Peter H. Schow
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Patent number: 7676729Abstract: A memory controller, system, and methods are disclosed. The system comprises a memory controller interconnected to a plurality of memory chips. Each memory chip stores data at a plurality of locations. The memory controller performs a sparing transaction comprising reading data from a given location of one or more of the memory chips including a first memory chip, writing the data to a given location of one or more of the memory chips including a second memory chip, wherein during writing, data from the first memory chip is written to the second memory chip, and allowing additional memory transactions directed to the memory chips between the start of reading and the end of writing unless the additional memory transaction is targeted to the given location. In a further embodiment, the sparing transaction comprises correcting errors in the data before writing the data.Type: GrantFiled: August 23, 2006Date of Patent: March 9, 2010Assignee: Sun Microsystems, Inc.Inventors: Charles Cheng, Robert E. Cypher, Michael W. Parkin
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Patent number: 7676634Abstract: Selective trace cache invalidation for self-modifying code via memory aging advantageously retains some of the entries in a trace cache even during self-modifying code events. Instructions underlying trace cache entries are monitored for modification in groups, enabling advantageously reduced hardware. Associated with each trace cache entry are translation ages that are determined when the entry is built by sampling current ages of memory blocks underlying the entry. When the entry is accessed and micro-operations therein processed, the translation ages of the accessed entry are compared with the current ages of the memory blocks underlying the accessed entry. If any of the age comparisons fail, then the micro-operations are aborted and the entry is invalidated. When any portion of a memory block is modified, the current age of the modified memory block is incremented. If one of the current ages overflows, then the entire trace cache is flushed.Type: GrantFiled: September 27, 2006Date of Patent: March 9, 2010Assignee: Sun Microsystems, Inc.Inventors: Leonard Eric Shar, Kevin Paul Lawton