Abstract: A CPU is provided with an ability to modify its operation, with respect to error correction, as a programmable feature. An error correction scheme is selected to be performed by the error correcting circuit. The compiled program may have intentionally introduced errors which are predictably corrected by the selected error correction scheme. When a program is compiled, the program is modified by the intentional insertion of errors which would result from the execution of the program. By providing error correction schema selected during program compilation, errors can be inserted in the program code, but are handled in a predictable manner by the error correction.

Abstract: A method for detecting a network cable connection state is disclosed. The method includes detecting a change of connection state of a connector using a sensor that resides in the connector and generating cable connection state information from the information supplied by the sensor. Cable connection state information is communicated to a connection state monitoring utility for facilitating network fault detection. The cable plug or socket may also contain an embedded processor, memory and unique identification.

Abstract: A method for maximizing page locality within a networking system operationally attached to a plurality of processing entities wherein each processing entity either shares or includes a corresponding memory hierarchy wherein each memory hierarchy has a table of pages temporally managed by access from the networking system is disclosed. The method includes providing at least one memory access channel to each memory hierarchy and moving information to and from pages in the memory hierarchy of a particular processing entity via its associated memory access channels.

Abstract: A method and apparatus for operating a computer system comprising a first and a second computing unit, the method comprising selecting a first clock frequency for operation of said first computing unit, and selecting a second clock frequency for operation of said second computing unit wherein said first and said second frequencies differ one from the other by at least a predetermined bandwidth.

Abstract: Disclosed is a method for eliminating dead code from a computer program using an operands graph generated from a flow graph of a computer program. In one embodiment of the present invention, the operands graph is traversed for any unused operands. Upon detection of any,unused operands, the instructions defining the unused operands are removed from execution.

Abstract: A modular computer system mechanical interconnection includes a primary chassis having a first opening and a secondary chassis attached to the primary chassis and having a second opening, wherein the first opening and the second opening are generally aligned. The apparatus further includes a backplate covering the aligned first opening and second opening.

Abstract: An arbiter is used so multiple users can use shared resources. The arbiter allocates at least one of the resources speculatively to one of the users for use during a particular access interval in the absence of a request for the resource from the user. The arbiter can also allocate one or more of the resources for use during the particular access interval in response to requests received by the arbiter for the resource(s). That is, a particular access interval may include both speculative and non-speculative allocation of resources by the arbiter.

Abstract: An apparatus and method for sharing a functional unit. In one embodiment, a processor may include instruction fetch logic configured to issue instructions, and a first functional unit configured to execute instructions issued from the instruction fetch logic and to execute operations issued from a second functional unit, where the operations are issued asynchronously with respect to the instructions. The second functional unit may be configured to provide one or more operands corresponding to a given operation to the first functional unit. The first functional unit may include temporary result storage configured to store a result of the given operation while the first functional unit executes a given instruction issued from the instruction fetch logic, and the first functional unit may be further configured to use the stored result as an operand of an operation issued subsequently to the given operation.

Abstract: In one embodiment, a processor comprises a cache shared by a plurality of threads in execution by the processor, an error detection unit coupled to the cache, and a fetch control unit. The error detection unit is configured to detect an error in data output by the cache responsive to an access corresponding to a first thread of a plurality of threads. Coupled to receive an indication of the error, the fetch control unit is configured to inhibit fetching for the first thread responsive to the error until the thread is redirected in response to the error and until the error is eliminated from the cache that includes the data.

Abstract: A computer system implementing transient blocking synchronization allows a memory location leased by a first process to be read-accessible to another process. In other words, more than one thread may have read-only type leases on a given memory location at a given time. Such “shared” leases expire when respective lease periods of the shared leases elapse.

Abstract: A protection domain for a set of errors is defined using an association between data and first integrity metadata to protect data traversing an input/output datapath. The datapath has a storage device as one endpoint and a first generation integrity point for a host as an opposite endpoint. A first sub-domain is defined within the protection domain using an association between the data and second integrity metadata to further protect a portion of the datapath having a second generation integrity point as one endpoint. In another aspect, a second sub-domain is defined within the protection domain using an association between the data and third integrity metadata further protect data traversing a portion of the datapath having a third generation integrity point as one endpoint. The first and second sub-domains are nested within the protection boundary and may be in a hierarchical relationship.

Abstract: In one embodiment, a node comprises at least one processor core and a plurality of coherence units. The processor core is configured to generate an address to access a memory location. The address maps to a first coherence plane of a plurality of coherence planes. Coherence activity is performed within each coherence plane independent of other coherence planes, and a mapping of the address space to the coherence planes is independent of a physical location of the addressed memory in a distributed system memory. Each coherence unit corresponds to a respective coherence plane and is configured to manage coherency for the node and for the respective coherence plane. The coherence units operate independent of each other, and a first coherence unit corresponding to the first coherence plane is coupled to receive the address if external coherency activity is needed to complete the access to the memory location.

Abstract: The present invention provides a method and apparatus for updating serial devices. The apparatus includes a plurality of serial registers. The apparatus further includes a device adapted to provide a signal and a plurality of parallel registers, wherein each of the parallel registers is adapted to access at least one of the plurality of serial registers at substantially the same time in response to detecting the signal.

Abstract: A method for inserting repeaters in an integrated circuit includes establishing a set of initial constraints for a given set of buses; assigning at least one repeater corresponding to each of the given set of buses based on the set of initial constraints; progressively relaxing the set of initial constraints to form a new set of constraints for a new set of buses and assigning at least one repeater corresponding to each of the new set of buses based on the new set of constraints; and routing assigned repeaters to each of the new set of buses in the integrated circuit.

Abstract: In general, the invention relates to a method for processing packets. The method includes receiving a first packet for a first target on a host. Prior to sending the packet to a Network Layer in the host, the method includes determining the first target of the first packet, obtaining a first target ID associated with the first target, obtaining a first virtual network stack (VNS) instance ID using the first target ID, and obtaining a first security configuration parameter using the first VNS instance ID. The method further includes sending the first packet to the Network Layer and processing the first packet in the Network Layer using the first security configuration parameter to obtain a first network processed packet.

Abstract: A product catalog is associated with a rules service allowing administrators to conduct examinations of a computer system's health. Rules services establish a set of rules to be run against a particular computer system and thereafter invoke a rules engine. The rules service accesses a product catalog to supply product reference data regarding each component of interest in the computer system. The product reference data supplies to the rules service structure and characteristics of the component's telemetry data as well as factors to consider with regard to component interaction. Once supplied with the product reference and input data the rules service conducts the analysis. When reference data is not available or fails to match parsed input data, a search is conducted to identify and retrieve reference data matching the structure and characteristics of the parsed input data. Upon finding a match the product catalog is updated with the new information.

Abstract: A method for tracing an instrumented program, including triggering an trap instruction in the instrumented program, transferring control of the instrumented program to a trap handler associated with the trap instruction, and emulating an instruction corresponding to the trap instruction in the trap handler, wherein the instruction relates to creating or dismantling a stack frame.

Abstract: A continuous data protection system, and associated method, for point-in-time data recovery. The system includes a consistency group of data volumes. A support processor manages a journal of changes to the set of volumes and stores meta-data for the volumes. A storage processor processes write requests by: determining if the write request is for a data volume in the consistency group; notifying the support processor of the write request including providing data volume meta-data; and storing modifications to the data volume in a journal. The support processor receives a data restoration request including identification of the consistency group and a time for data restoration. The support processor uses the data volume meta-data to reconstruct a logical block map of the data volume at the requested time and directs the storage processor to make a copy of the data volume and map changed blocks from the journal into the copy.

Abstract: Embodiments of the present invention provides a system that optimizes a regression model which predicts a signal as a function of a set of available signals. These embodiments use a genetic technique to optimize the regression model, which involves using a portion of the sample signals used to generate each parent regression model from a pair of best-fit parent regression models to generate a child regression model. In addition, in embodiments of the present invention, the system introduces “mutations” to the set of sample signals used to create the child regression model in an attempt to create more robust child regression models during the optimization process.

Abstract: A memory system comprising router nodes. A plurality of router nodes are configured to route data between a memory controller and memory modules. The topology of the system comprises a hierarchy of one or more levels. Each of the levels includes one or more router nodes which may be configured to forward received data to another router node at the same level, or forward received data to a next lower level in the hierarchy. Router nodes in the system are configured to correspond to a particular level and position within the hierarchy. The memory controller generates a broadcast transaction to router nodes in the system. In response to receiving the transaction, the router nodes configure their internal routing mechanisms. Subsequently, the controller generates a memory access which is then routed by the router nodes to the target memory modules. Routing is such that memory modules not targeted by the memory access do not see the memory access.