Abstract: An intelligent queue may be used to facilitate communication among a set business application programs. In one embodiment, the intelligent queue may interact with a variety of business application programs providing consistent service behaviors across a variety of data store products. The intelligent queue provides extended message storage, efficient journalling, interoperability with other intelligent queues, load balancing, once-only processing, as well as detailed message state information that tracks the status of each message from both the sender and the recipient's perspective.

Abstract: A computer-based system that permits a service-provider to monitoring other computer systems includes a plurality of relays. A monitored relay collects data from one or more monitored computers in the system. This data is forwarded through a secure communication pipeline implemented by the monitoring system to a forwarding relay. The forwarding relay controls data flow between a service provider node and the monitored relays, and includes an instrumentation process that collects data regarding one or more message threads in the relay and sends the data downstream to a service provider system. Computers at the service provider node analyze the data to generate meaningful information about the monitored system, which can be accessed by the service provider or by the owner/operator of the computer system. In addition, the information may be used to generate notices or alarms of specific events.

Abstract: An estimate is calculated of the throughput of a multi-threaded processor having N threads based on measured miss rates of a cache memory associated with the processor by calculating, based on the cache miss rates a probability that the processor is in a state with one thread running, a probability that the processor is in a state with two threads are running and continuing to a probability that the processor is in a state with N threads running, multiplying each probability by a measured throughput of the processor when it is in the corresponding state and summing the resulting products. This estimate may also be corrected for bus delays in transferring information between the cache memory and main memory. The estimate can be used for thread scheduling in a multiprocessor system.

Abstract: A coherence prediction mechanism includes a synchronization manager and a plurality of access predictors. The synchronization manager maintains one or more sequence entries, each sequence entry indicating a sequence in which a corresponding data block is accessed by two or more processing elements of a multiprocessor system. An access predictor provides a prediction to the synchronization manager identifying a next data block to be accessed by a corresponding processing element. In response to an indication of an access to a particular data block from a first processing element, the synchronization manager accesses a sequence entry corresponding to the particular data block and sends an identification of a next processing element expected to access the data block to the first processing element. The first processing element may use the identification to perform one or more speculative coherence actions.

Abstract: A deque of a local process in a memory work-stealing implementation may use one or more data structures to perform work. If the local process attempts to add a new value to its deque's data structure when the data structure is full (i.e., an overflow condition occurs), the contents of the data structure are copied to a larger allocated data structure (e.g., an array of greater size than an original array). The entries in the original, smaller-sized data structure are copied to exact positions in the now-active, larger-sized data structure. By this technique, the local process is thus provided with space to add the new value.

Abstract: A system controller module is operable to monitor system operation in a system that can include a further such system controller module. The system controller module can include system controller storage and can be operable to maintain system parameters therein. At least a predetermined part of the system controller storage can include a plurality of domains. A check code (e.g., a pseudo CRC) can be generated for each domain such that equivalence between check codes for a domain in the system controller storage and a corresponding domain in further storage of a further system controller module is indicative of the domains concerned being in synchronism.

Abstract: A method for inserting flip-flops in an interconnect is provided such that a cycle time constraint for the interconnect is satisfied. First of all, a flop is inserted at an initial placement at a node along a signal path of the interconnect such that a downstream delay relative to the initial placement of the flop is not greater than the cycle time constraint for the net. Secondly, the initial placement of the flop is optimized such that a delay difference, defined by a downstream delay minus an upstream delay, relative to an optimal placement at a downstream node along the signal path of the net is not greater than zero. The disclosed method can also satisfy the flop stage requirement and/or a minimum number of flops requirement for an interconnect.

Abstract: A system may include a plurality of nodes. Each node may include one or more active devices coupled to one or more memory subsystems. Each active device in one of the plurality of nodes includes a memory management unit configured to receive a virtual address generated within that active device and to responsively output a global address and associated information that identifies a translation function. The memory subsystem in the one of the plurality of nodes is configured to apply the translation function identified in the information to the global address to generate a local physical address.

Abstract: Obfuscating an application program comprises reading a first application program, determining an application program instruction location permutation that transforms the first application program into an obfuscated application program having at least one application program instruction stored at a memory location that is based at least in part on a permutation of the memory location where the corresponding application program instruction is stored in the first application program, applying the application program instruction location permutation to the first application program to create an obfuscated application program, and sending the obfuscated application program.

Abstract: One embodiment of the present invention provides a system that assigns jobs to a system containing a number of central processing units (CPUs). During operation, the system captures a current state of the system, which describes available resources on the system, characteristics of jobs currently being processed, and characteristics of new jobs waiting to be assigned. The system then uses the system state to estimate a long-term benefit to the system of not oversubscribing the system. If the benefit from oversubscribing the system with a new job exceeds the benefit from not oversubscribing the system, the system oversubscribes the system with the new job.

Abstract: A method for performing a boot from a storage network. A first server stores boot configuration information linked to or searchable by a network device identifier. A second server stores intermediate boot modules configured to perform input/output (I/O) functions in the storage network. At the first server, a request from a network device is received that includes a hardware identifier for the network device. The first server uses the hardware identifier to retrieve boot configuration information for the network device that is transferred to the network device and that includes a location in the storage network of a disk device containing an operating system image and the second server address. The network device obtains the boot modules from the second server and runs them using the disk device location to read the operating system image from the disk device using storage I/O functions in the boot modules.

Abstract: An apparatus for cooling a microprocessor includes a first thermal interface material layer; a lid that encases the first thermal interface material layer and the microprocessor; a second thermal interface material layer applied to a top of the lid; at least one configurable diamond pin; at least one heat pipe; and a heat sink structure. At least one diamond pin is configured to displace junction temperature on a hot spot location of the microprocessor. The heat sink structure and at least one heat pipe are configured atop the second thermal interface material layer.

Abstract: A system and method for managing threads and thread requests in an application server. If the application is a thread-partitioned application with a request, the thread manager may determine if an application thread array for the application has less than the maximum number of threads partitioned for the application. If it does, the thread manager may retrieve a thread from the main thread pool, and assign it to the request. If it does not, the thread manager may determine if there are any free threads in an application thread array, and if there are, one of the free threads in the application thread array may be assigned to the request. If there are no free threads available in the application thread array, the request may be added to a ready queue.

Abstract: A system and method for secure generation and distribution of digital encryption keys is disclosed. The system may also be used to protect and distribute other types of secure information, including digital, audio, video, or analog data, or physical objects. The system may include a tamper-respondent secure token device, which may be configured to destroy or disable access to the secure information contained therein in response to attempts to physically or electronically breach the device. Outputs may be provided in a secure manner through various interfaces without using electricity (wires) or electromagnetic radiation. Inputs may be provided in a secure manner, including through the use of a gesture-based input interface. Destruction or disablement of the device and/or its secure contents may be provided upon detection of tamper attempts or upon input of a self-destruct command. Proof of the destruction or disablement of the device or its contents may be provided.

Abstract: Disclosed herein are methods and systems for generating test vectors for use in verification of a circuit design and for hardware testing on a fabricated circuit representative of the circuit design. The system and methods can systematically and automatically perform functional and structural testing on selected paths of the circuit design and, in turn, generate one or more test vectors to increase PDT test coverage using the results of the structural test on the selected path.

Abstract: Functionality from an object file can be incorporated into an already existing binary file. Functions from the object file can be intelligently inserted into the binary file with the guidance of control flow analysis of both the binary file and the object file. Symbols not defined in the symbol table of the binary file are added to the symbol table of the binary file. When symbols of the object file and the binary file overlap, then priority is given to the object file symbol definitions. The ability to incorporate functionality from an object file into an existing binary file reduces logistical overhead and provides flexibility in code development and maintenance.

Abstract: A method for maximizing revenue generated from a plurality of service level agreements (SLAs) that includes receiving a first subset of the plurality of SLAs for executing a first plurality of jobs, wherein each SLA in the first subset specifies a first maximum requested delay that is greater than an initial minimum offered delay, and wherein a price of each SLA in the first subset is defined by the maximum requested delay and a price/delay function, calculating a first expected revenue from executing the first subset, and optimizing a second subset of the plurality of SLAs by replacing the initial minimum offered delay on the initial price/delay function with a new minimum offered delay based on the expected revenue, wherein each SLA in the second subset specifies a second maximum requested delay that is greater than the new minimum offered delay.

Abstract: Methods and systems consistent with the present invention allow a program designer to conveniently specify and support watchdog checking of a program under development. The resulting programs are more robust than programs developed without watchdog support. The method and systems provide a convenient, automated mechanism for adding watchdog support to a program. Thus, a developer need not incur the substantial time and effort costs that would be associated with manually designing and configuring separate watchdog programs. Rather, the methods and systems provide substantial assistance to the developer in designing a robust program.

Abstract: A system may include a plurality of nodes. Each node may include one or more active devices coupled to one or more memory subsystems. An active device included in one of the nodes includes a memory management unit configured to receive a virtual address generated within that active device and to responsively output a global address identifying a coherency unit. A portion of the global address identifies a translation function. A memory subsystem included in the node is configured to perform the translation function identified by the portion of the global address on an additional portion of the global address in order to obtain a local physical address of the coherency unit. Each active device included in the node is configured to use the portion of the global address identifying the translation function when determining whether a local copy of the coherency unit is currently stored in a cache associated with that active device.

Abstract: An invention is provided for displaying two-dimensional data on small screen devices. The invention includes providing a first data set display section on a screen, which is capable of presenting a list of entries in a first data set. In addition, a second data set display section is provided on the screen. The second data set display section is capable of presenting a particular entry from a second data set associated with a selected entry from the first data set. In operation, a new entry from the second data set is presented in the second data set display section in response to receiving a navigation command related to the second data set. The new entry is associated with the selected entry from the first data set.