Abstract: A method to communicate data is disclosed which includes communicating a virtual address to a translation lookaside buffer (TLB) and translating the virtual address to a physical address of a computer memory. The method also includes loading the physical address translated by the TLB into a register within a processor and transmitting the data from the physical address to a destination computing device.

Abstract: In one embodiment, a cache comprises a cache memory and a cache control circuit coupled to the cache memory. The cache memory is configured to store a plurality of cache blocks and a plurality of cache states. Each of the plurality of cache states corresponds to a respective one of the plurality of cache blocks. The cache control circuit is configured to implement a cache coherency protocol that includes a plurality of stable states and a transient state The transient state may be used in response to any request from a local consumer if completing the request includes a change between the plurality of stable states and making the change includes transmitting at least a first communication to maintain coherency on an interconnect.

Abstract: A method for providing management information about an asset includes obtaining a job from a job queue, determining the asset type of the asset from the job, triggering a protocol handler based on a data acquisition (DAQ) definition associated with the asset type and the job, receiving management information about the asset from the protocol handler, identifying at least one registered listener of the management information from the DAQ definition, where at least one registered listener includes an information model class instance, and notifying the at least one registered listener of the management information.

Abstract: A method for inferring an altitude of a computing device, involving monitoring variable data associated with a plurality of variables measured within the computing device, inferring the altitude of the computing device using the measured plurality of variables in a multivariate correlation function, and controlling operation of the computing device based on the inferred altitude.

Abstract: The invention provides a central office metaphor to computing, where features and functions are provided by a one or more servers and communicated to an appliance terminal through a network. Data providers are defined as “services” and are provided by one or more processing resources. The services communicate to display terminals through a network, such as Ethernet. The terminals are configured to display data, and to send keyboard, cursor, audio, and video data through the network to the processing server. Functionality is partitioned so that databases, server and graphical user interface functions are provided by the services, and human interface functionality is provided by the terminal. Communication with the terminals from various services is accomplished by converting disparate output to a common protocol. Appropriate drivers are provided for each service to allow protocol conversion. Multiple terminals are coupled to the network.

Abstract: A developer is provided with an emulation tool, which approximates speed conditions of an application executing on a target device, for example a MIDlet executing on a mobile information device, by matching network operations of a development platform to the lesser performance capabilities of the target device. The developer is thereby enabled to optimize an application's network usage early in its development. The time required to perform communications operations in the development environment is increased sufficiently to permit an application developer to more accurately emulate the target device.

Abstract: A method and apparatus for retrieving instructions to be processed by a microprocessor is provided. By pre-fetching instructions in anticipation of being requested, instead of waiting for the instructions to be requested, the latency involved in requesting instructions from higher levels of memory may be avoided. A pre-fetched line of instruction may be stored into a pre-fetch buffer residing on a microprocessor. The pre-fetch buffer may be used by the microprocessor as an alternate source from which to retrieve a requested instruction when the requested instruction is not stored within the first level cache. The particular line of instruction being pre-fetched may be identified based on a configurable stride value. The configurable stride value may be adjusted to maximize the likelihood that a requested instruction, not present in the first level cache, is present in the pre-fetch buffer. The configurable stride value may be updated manually or automatically.

Abstract: In one embodiment, an apparatus comprises a plurality of core logic blocks, a plurality of first event blocks, and a second event block. Each of the plurality of core logic blocks is configured to generate one or more indications of one or more events. Each first event block of the plurality of first event blocks is coupled to a respective core logic block of the plurality of core logic blocks to receive the one or more indications from the respective core logic block. Each first event block comprises at least one register configured to record which events have been indicated by the respective core logic block. Coupled to the plurality of first event blocks, the second event block is configured to initiate one or more actions responsive to one or more events detected in one or more of the plurality of first event blocks.

Abstract: One embodiment of the present invention provides a system that selects bases to form a regression model for cache performance. During operation, the system receives empirical data for a cache rate. The system also receives derivative constraints for the cache rate. Next, the system obtains candidate bases that satisfy the derivative constraints. For each of these candidate bases, the system: (1) computes an aggregate error E incurred using the candidate basis over the empirical data; (2) computes an instability measure I of an extrapolation fit for using the candidate basis over an extrapolation region; and then (3) computes a selection criterion F for the candidate basis, wherein F is a function of E and I. Finally, the system minimizes the selection criterion F across the candidate bases to select the basis used for the regression model.

Abstract: An apparatus multiplies a first and a second binary polynomial X(t) and Y(t) over GF(2), where an irreducible polynomial Mm(t)=tm+am?1tm?1+am?2tm?2tm?2+ . . . +a1t+a0, and where the coefficients ai are equal to either 1 or 0, and m is a field degree. The degree of X(t)<n, and the degree of Y(t)<n, and m?n. The apparatus includes a digit serial modular multiplier circuit coupled to supply a multiplication result of degree ?m of a multiplication of the first and second binary polynomials. The digit serial modular multiplier circuit includes a first and second register, each being ?n bits. A partial product generator circuit multiplies a portion of digit size d of contents of the first register and contents of the second register. The partial product generator is also utilized as part of a reduction operation for at least one generic curve.

Abstract: A method for compiling a logic design includes inputting a logic design and an input file into a plurality of compilers, respectively, where the logic design comprises a plurality of modules, compiling separately the plurality of modules into a plurality of object files, and linking the plurality of object files to execute the logic design.

Abstract: A deque of a local process in a memory work-stealing implementation may use one or more data structures to perform work. If the local process attempts to add a new value to its deque's circular array when the data structure is full (i.e., an overflow condition occurs), the contents of the data structure are copied to a larger allocated circular array (e.g., a circular array of greater size than the original circular array). The entries in the original, smaller-sized circular array are copied to positions in the now-active, larger-sized circular array, and the system is configured to work with the newly activated circular array. By this technique, the local process is thus provided with space to add the new value.

Abstract: In an embodiment of the present invention, at a Deployer level, an application software component is provided with a tree representation 510 of objects it contains. An object is a leaf node, with the attributes of the object being in nexus between the root and the leaf node. An accessor object 511 has methods to access the tree 510. In one embodiment of the present invention, at an administrator level, a handler object 611 in turn accesses accessor object 511. Handler object 611 may be part of a handler home object 619. Client applications 710 have lookup services 711 to access handler objects like 611, e.g. via a lookup home object 719, and handler home object 619.

Abstract: A method for inducing multi-threading in software code may use blocks of code as the basis for scheduling and to suggest concurrent execution for each block. The method may comprise marking one or more blocks of code in an application coded for sequential execution to generate marked code. The marking may comprise inserting a marker at each of the one or more blocks to suggest that block for potential concurrent execution. Concurrent code may be generated from the marked code. Generating the concurrent code may comprise analyzing the marked code to estimate performance benefits of concurrently executing the marked blocks of code and determine which marked blocks would meet a performance benefit threshold if executed concurrently. Generating the concurrent code may also comprise transforming one or more of the marked blocks into corresponding concurrently executable tasks. The method may include scheduling one or more of the concurrently executable tasks.

Abstract: A movable data center comprising a portable enclosure in which a data processing module is operatively disposed. The data processing module is assembled onto a rack located in the enclosure that is movable between and operative position and a service position. A heat exchange module is arranged in the enclosure in air flow communication with the data processing module on the rack. The rack may be moved from the operative position in which the rack is in air flow communication with the heat exchange module to the service position in which the rack is not in air flow communication with the heat exchange module.

Abstract: Offloading data coherence operations from a primary processing unit(s) executing instantiated code responsible for data coherence in a shared-cache cluster to a data coherence offload engine reduces resource consumption and allows for efficient sharing of data in accordance with the data coherence protocol. Some of the data coherence operations, such as consulting and maintaining a directory, generating messages, and writing a data unit can be performed by a data coherence offload engine. The data coherence offload engine indicates availability of the data unit in the memory to the appropriate instantiated code. Hence, the instantiated code (the corresponding primary processing unit) is no longer burdened with some of the work load of data coherence operations. Migration of tasks from a primary processing unit(s) to data coherence offload engines allows for efficient retrieval and writing of a requested data unit.

Abstract: A method for controlling a plurality of fans operatively disposed in a shipping container. The fans are arranged in a plurality of banks within a closed fluid path. Each bank has a sub-set of the fans arranged in a plurality of horizontal layers. Two banks form an adjacent pair in the closed fluid path if a fluid exiting one of the two banks next enters the other of the two banks. The method includes determining a proposed fluid flow rate for each of the banks. The method also includes modifying each of the flow rates by a respective scaling factor such that the flow rates for each adjacent pair satisfy a continuity criteria. The method further includes controlling the fans based on the modified flow rates.

Abstract: Apparatus, systems, and methods are provided for testing the integrity of electrical interconnections in electronic systems. Apparatus may be constructed by modifying a substrate designed for deployment in an end-use product by shorting together multiple contacts on one side of it. Such vehicles may be used to test the characteristics of interconnections between the vehicle and its support, the shorted contacts enabling testing of individual interconnects under both DC and AC conditions. A system for testing the interconnects may include the modified substrate, an input signal generator, and an output signal monitor.

Abstract: A movable data center is disclosed that comprises a movable enclosure having partitions that define a closed-loop air flow path. A plurality of fans and a plurality of data processing modules are disposed in the air flow path. A pipe network is disposed within the enclosure that includes a chilled water supply pipe that receives chilled water from a source of chilled water. A water return pipe is provided that circulates water back to the source of chilled water. A plurality of heat exchange modules is installed in the enclosure in the air flow path. The heat exchange modules receive the chilled water from the chilled water supply pipe. Each of the heat exchange modules has a water circulation tube that connects the chilled water supply pipe to the return water pipe.