Abstract: A method of a copying data includes a cache subsystem loading data to be copied from a first address, and placing the data in a cache as if the data had been loaded from a second address. The data can then subsequently be written to the second address to effect the copy.

Abstract: A method and apparatus for profiling a heap. According to the method, a flexible and comprehensive general-purpose profiling interface that uniformly accommodates a wide variety of memory allocation and garbage collection methods is used. The profiling interface, among other things, employs a set of virtual machine profiling interface events that support all known types of garbage collection methods.

Abstract: A system and method for performing viewport clipping for multiple viewports using a pipeline. The pixel address coordinates are compared against boundaries of a first viewport window. The results of this comparison, along with the pixel address coordinates, are registered and passed on to the next pipeline stage. There, the pixel address coordinates are compared against the boundaries of a second viewport window. The comparison results are combined with those passed from the previous stage, and the results are again registered. This scheme is repeated until the pixel has been tested against all the viewport window boundaries, with the intermediate results being combined into a single result indicative of whether the pixel is to be passed to the subsequent stages of the graphics pipeline or clipped.

Abstract: A method and apparatus is disclosed for maintaining coherency between a primary cache and a secondary cache in a directory-based cache system. Upon identifying a parity error in the primary cache, a tag parity packet and a load instruction are sent from the primary cache to the secondary cache. In response to the tag parity packet, each tag entry in the secondary cache that is associated with the parity error is invalidated. Upon receiving an acknowledgment of receipt of the tag parity packet, the primary cache functions to invalidate each tag entry in the primary cache that is associated with the parity error. Then, the secondary cache communicates data requested in the load instruction to the primary cache.

Abstract: The present invention relates to computer systems and methods for providing a memory buffer for use with native and platform-independent software code. In a particular embodiment, the method includes providing a first software program compiled to platform-independent code for execution in a first process of the computer system, providing a second software program compiled to native code for execution in a second process of the computer system, and sending a message from the first process to the second process to request a memory buffer. In another particular embodiment, the computer system includes a processor and a memory. The computer system includes a first process to execute a first software program coded in a safe language, a second process to execute a second software program coded in an unsafe language, and an inter-process communication mechanism that allows data message communication between the first process and the second process.

Abstract: A method for configuration of a program with a plurality of configuration variables to operate on a computer system that includes obtaining a plurality of priority semantics for the plurality of configuration variables, wherein the plurality of priority semantics are heterogeneous, assigning a value for each of the plurality of configuration variables based on the plurality of priority semantics, and configuring the program using the value to operate on the computer system.

Abstract: A method for creating a histogram from a plurality of data elements that includes identifying a lower extreme range counter and an upper extreme range counter for the plurality of data elements, incrementing a value counter when the value counter corresponds to a value of a first data element in the plurality of data elements, incrementing the lower extreme range counter, wherein incrementing the lower extreme range counter is performed when a value of a second data element in the plurality of data elements is less than a pre-defined lower boundary, incrementing the upper extreme range counter, wherein incrementing the upper extreme range counter is performed when a value of a third data element in the plurality of data elements is greater than a pre-defined upper boundary, and creating the histogram from the value counter, the lower extreme range counter, and the upper extreme range counter.

Abstract: Transactional programming promises to substantially simplify the development and maintenance of correct, scalable, and efficient concurrent programs. Designs for supporting transactional programming using transactional memory implemented in hardware, software, and a mixture of the two have emerged recently. Unfortunately, conventional debugging programs are often inadequate when employed in relation to code that employs transactional memory and new or modified techniques are needed. We describe techniques whereby certain facilities of a transactional memory implementation can be leveraged to provide replay debugging. With replay debugging, the user can examine a partial or complete execution of an atomic block after it has happened—for example, right before the execution commits. Moreover, in some cases the user can modify the replayed execution, and decide to commit the new modified execution instead of the original replayed one.

Abstract: Transactional programming promises to substantially simplify the development and maintenance of correct, scalable, and efficient concurrent programs. Designs for supporting transactional programming using transactional memory implemented in hardware, software, and a mixture of the two have emerged recently. However, various features and capabilities for debugging programs executed using transactional memory are absent from conventional debuggers. Because transactional memory implementations provide the “illusion” of multiple memory locations changing value atomically, there are challenges involved with integrating debuggers with such programs to provide the user with a coherent view of program execution. For instance, when execution is halted for debugging, a user may request to view a transactional variable or memory location. The transactional variable or memory location may have a pre-transaction value and a tentative value.

Abstract: A integrated circuit housing includes a first clamping hardware, a second clamping hardware operatively connected to the first clamping hardware, and an integrated circuit stack comprising a top portion and a bottom portion, wherein the first clamping hardware contacts the top portion and the second clamping hardware contacts the bottom portion, and wherein a first shim is interposed between the bottom portion and the second clamping hardware.

Abstract: A system includes electronic equipment, a device arranged to cool air using a refrigerant, the device secured to one of a top side and a bottom side of the electronic equipment, and a housing arranged to enclose the electronic equipment and the device, where the cooled air is propagated from one of the top side and the bottom side of the electronic equipment to the other one of the top side and the bottom side of the electronic equipment.

Abstract: Transactional programming promises to substantially simplify the development and maintenance of correct, scalable, and efficient concurrent programs. Designs for supporting transactional programming using transactional memory implemented in hardware, software, and mixtures of the two have emerged recently. However, conventional debuggers do not provide features and capabilities that could be desirable for debugging programs executed using transactional memory. For example, conventional debuggers are not adapted to provide a coherent or consistent view of variables in a system that employs transactional memory. Because transactional memory implementations provide the “illusion” of multiple memory locations changing value atomically, while in fact they do not, there are challenges involved with integrating debuggers with such programs to provide the user with a coherent view of program execution.

Abstract: Methods and systems consistent with the present invention provide a mechanism for accepting extended amounts of data in a layered network protocol. The methods and systems thus allow the network protocol to more efficiently receive data and forward the data to the correct entity. As a result, the programs experience greater network data throughput. The methods and systems may be implemented in widely accepted Internet Protocol (IP) and Transmission Control Protocol (TCP) networks.

Abstract: In one embodiment, a storage subsystem includes a plurality of storage arrays each including a plurality of storage devices. The storage subsystem also includes a plurality of array controllers each coupled to one or more of the plurality of storage arrays. One or more of the arrays corresponds to a failure group. Each array controller may create a storage volume including storage devices belonging to one or more of plurality of storage arrays. In addition, the storage subsystem includes a redundancy controller that may be configured to implement N+K redundancy. The redundancy controller includes configuration functionality that may determine a number of redundant system data blocks to be stored on different storage devices for a given stripe of data that is dependent upon particular values of N and K and upon physical system configuration information.

Abstract: One embodiment of the present invention provides a system that supports concurrent accesses to a skip list that is lock-free, which means that the skip list can be simultaneously accessed by multiple processes without requiring the processes to perform locking operations. During a node deletion operation, the system receives reference to a target node to be deleted from the skip list. The system marks a next pointer in the target node to indicate that the target node is deleted, wherein next pointer contains the address of an immediately following node in the skip list. This marking operation does not destroy the address of the immediately following node, and furthermore, the marking operation is performed atomically and thereby without interference from other processes.

Abstract: A system and method for dynamically disabling partially streamed content may include a server receiving a request from a client. A session may be initiated or continued in response to the request. The server may begin to stream content to the client as a partial fulfillment of the request. While processing the request, the server may determine if the partially streamed content should be disabled. In response to determining that the partially streamed content should be disabled, the server may disable the partially streamed content without terminating the session. Disabling the partially streamed content may involve preventing the client from accessing content referenced by a hyperlink associated with the partially streamed content, or may involve the use of a controller located on the client to disable content streamed to the client.

Abstract: Embodiments may provide mechanisms for representing trust between peers or systems in decentralized networking environments including peer-to-peer networking environments. Trust may include both direct trust between two peers and trust in a pipeline of peers along which codat may be passed. Embodiments may provide a mechanism for a peer to represent and rate the trustworthiness of other peers as providers of codat relevant to the peer's interest. To evaluate trust in another peer as a provider of codats in the area of interest, trust may be represented with two components, confidence and risk. Embodiments may provide mechanisms for measuring the components and determining trust from the components. Embodiments may also provide mechanisms for feeding back trust information to the providing peer and for propagating trust information to other peers.

Abstract: A method for creating a histogram from a plurality of data elements that includes specifying a plurality of internal buckets, wherein each internal bucket of the plurality of internal buckets represent values between an internal minimum value and an internal maximum value, wherein a plurality of differences of the internal minimum value and the internal maximum value of each internal bucket are heterogeneous, populating the plurality of internal buckets with the plurality of data elements based on the internal minimum value and the internal maximum value of each internal bucket to obtain a plurality of populated internal buckets, and outputting the histogram from the plurality of populated internal buckets.

Abstract: Prefetch information is generated for multi-block indirect memory access chains. A method may include selecting a chain of indirect memory accesses of a procedure, the chain comprising a head access that does not depend for its address on another prefetch candidate memory access within the procedure and an indirect access that depends for its address on the head access. The method may further include determining a prefetch-ahead value for the chain, and generating a load operation corresponding to the head access that specifies a target memory address that is dependent upon the prefetch-ahead value and an address of the head access. The method may further include, for a terminal indirect access of the chain, generating a respective prefetch operation that is dependent for its address computation on results of preceding load operations in the same manner as its corresponding terminal indirect access depends upon preceding accesses in the chain.

Abstract: The use of a token-based memory protection technique may provide memory protection in a computer system employing memory virtualization. A token-based memory protection technique may include assigning a unique identifier to an application, process, or thread, and associating the identifier with a block of memory allocated to that application, process, or thread. Subsequent to assigning the identifier, a packet requesting access to that block of memory may include a token to be compared to the identifier. A memory controller may be configured to associate the identifier with the block of memory and to compare the token in the memory request packet to the identifier before granting access. If a second block of memory is subsequently allocated to the application, process, or thread, the identifier may be disassociated with the first block of memory and associated with the second block of memory.