Abstract: A system and method for ranking objects by a likelihood of possessing a property is disclosed. The system can be used, for example, to assist in the determination of system events, such as, e.g., computer system failures, based upon an analysis of customer service reports or the like.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide for predicting system failure based on pattern recognition of subcomponent exposure to failure. A dataset is generated that has at least one exposure level to failure of a computer-based system and a corresponding rule identifier of a rule used to calculate the exposure level. The rule asynchronously receives information about the computer-based system and calculates the exposure level based on the received information. The generated dataset is compared to a previously generated dataset by comparing the at least one exposure level of the dataset to an at least one exposure level with the same rule identifier in the previously generated dataset, where the previously generated dataset is associated with a known problem with the computer-based system.

Abstract: A method for a client to access data files residing on a first data server through a network includes coupling a heterogenous proxy server to the first data server through a first local network protocol, selectively receiving at the heterogeneous proxy server a data file from the first data servers by employing the first local network protocol, translating the data file into a format compatible with transmission through the network, and transmitting the translated data file to the client across the network.

Abstract: A method and apparatus for facilitating the determination of a status of an asynchronous memory (e.g., how full or empty the memory is). A write pointer to the memory is maintained in a first clock domain; a read pointer is maintained in a second clock domain. The pointers are maintained in a non-binary code format promoting minimum bit transitions as the pointers increment (e.g., Gray code). Each pointer is transmitted to the other clock domain through synchronizers. Each synchronizer comprises multiple sets of D flip-flops. In each clock domain, the write pointer and read pointer values are converted to mathematically useful formats (e.g., binary), and their difference is calculated. The difference indicates how much space in the memory is or is not used, and may be compared to a non-zero threshold.

Abstract: One embodiment of the present invention provides a system that facilitates configuring selected methods for instrument-based profiling at run-time. The system first identifies a root method in a target application, wherein only methods that are reachable from the root method during execution of the target application are to be instrumented. The system then instruments the root method. Next, while subsequently executing a given instrumented method, the system determines if the given instrumented method is about to be executed for the first time. If so, the system instruments any methods that are called by the given instrumented method, are loaded, and have not been instrumented before.

Abstract: One embodiment of the present invention provides a system that facilitates aligning a first signal with a second signal in a manner that optimizes a correlation between the first signal and the second signal. The system starts by receiving a set of signals, including the first signal and the second signal. The system then determines a correlation between the first signal and the second signal. Next, the system adjusts an alignment between the first signal and again determines a correlation between the first signal and the second signal. If the correlation is greater with the alignment adjustment, the system adjusts the alignment between the first signal and the second signal. This process of adjusting the alignment is repeated for different alignments to find an optimal alignment. Hence, the present invention operates effectively for signal sources which may be independently speeding up and slowing down with respect to each other while under surveillance.

Abstract: A method for determining misalignment between two semiconductor dies is described in which signals are transmitted through a first subset of an array of proximity connectors that are proximate to a surface of one of the semiconductor dies and received through a second subset of an array of proximity connectors that are proximate to a surface of the other semiconductor die. A spatial beat frequency is determined from the received signals. This spatial beat frequency corresponds to misalignment-induced aliasing of spatial frequencies associated with the first subset of the array of proximity connectors and the second subset of the array of proximity connectors. The misalignment is then determined using the spatial beat frequency.

Abstract: The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide stronger synchronization operations, for example, ones that atomically modify one memory location while simultaneously verifying the contents of others. We provide a simple and highly efficient nonblocking implementation of such an operation: an atomic k-word-compare single-swap operation (KCSS). Our implementation is obstruction-free. As a result, it is highly efficient in the uncontended case and relies on contention management mechanisms in the contended cases. It allows linked data structure manipulation without the complexity and restrictions of other solutions.

Abstract: One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store.

Abstract: One embodiment of the present invention provides a system that tunes state-based scheduling policies, wherein the system contains a number of central processing units (CPUs). During operation, the system recurrently estimates a long-term benefit to the system by feeding a system state as input to a parametric value function and computing an output from the parametric value function. The system makes scheduling decisions for the CPUs based on the estimated long-term benefit to the system. The system also tunes a parameter of the parametric value function based on current and previously estimated long-term benefit to the system, thereby facilitating more effective scheduling policies.

Abstract: A method, and associated system, for performing distributed computing. The method includes linking a user node to a communications network including a processor with a processing capacity, memory, and a browser for viewing documents provided over the network. The method includes operating the browser to request a document from a server linked to the network and then receiving a host document or host web page. The browser views the host document and loads a distributed application that requests work from the server. The user node receives work units from a distributed computing project associated with the distributed application. The distributed application is run by the processor using excess capacity to process the work unit to generate a result. The method determines if the browser is still viewing the host document and the processor is available. The browser may be replaced with a user application that provides distributed computing.

Abstract: A system for correcting the intensities of pixels supplied to a projector. An image generated by the projector has a number of regions formed by the overlapping of the image with one or more other images generated by one or more other projectors. The system includes: a first unit configured to generate a horizontal scaling value; a second unit configured to generate a vertical scaling value; a first multiplier configured to multiply the horizontal scaling value and the vertical scaling value to obtain a scaling coefficient, and a set of one or more additional multipliers configured to multiply components of an input pixel by the scaling coefficient to determine components for an output pixel. The first unit and second unit compute their respective scaling values in a way that allows for regions whose boundaries non-aligned in the vertical direction.

Abstract: A space-incremental garbage collector performs marking operations that are usually separated by several collection increments. It uses the marking results to compute collection-efficiency metrics for regions into which it treats the heap as divided. It bases its selection of regions for successive increments' collection sets on the metrics' values, whose computations also depend on the sizes of the regions' “remembered sets,” i.e., on the lists of locations where references to objects in those regions have been observed. Although the remembered-set sizes therefore potentially change between collection increments, the collector re-computes metrics in most collection increments for only a subset of the regions. It selects the subset in accordance with a sorting of all regions that it performed at the end of the most recent completed marking operation.

Abstract: A system and method for performing speculative initialization of application models for a cloned runtime system process is presented. A class loader is created for each application model. Each such class loader includes a representation of at least one class from a source definition provided as object-oriented program code and associated with the application model. A master runtime system process is executed. The representation of the class loader is interpreted, instantiated and warmed up as an application model specific class loader instance in a memory space of the master runtime system process. The memory space is cloned as a child runtime system process responsive to a process request and the child runtime system process is executed. The child runtime process selects one such application model specific class loader instance, rather than creating a new application model specific class loader instance.

Abstract: Apparatus and method for automatically generating resource types for installation on nodes of a clustered computer system. The wizard provides a user interface for inputting user specified parameters relating to the configuration of the clustered computer system and the application. Based on the input information, the wizard automatically generates resource types that start, stop and monitor execution of the application on nodes of clustered computer system. The generated resource types can be provided as a software package for easy installation on nodes of the clustered computer system.

Abstract: One embodiment of the present invention provides a system which facilitates eliminating a restart penalty when reissuing deferred instructions in a processor that supports speculative-execution. During a normal execution mode, the system issues instructions for execution in program order, wherein issuing the instructions involves decoding the instructions. Upon encountering an unresolved data dependency during execution of an instruction, the processor performs a checkpointing operation and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. When an unresolved data dependency is resolved during execute-ahead mode, the processor begins to execute the deferred instructions in a deferred mode. In doing so, the processor initially issues deferred instructions, which have already been decoded, from a deferred queue.

Abstract: A method of testing a plurality of embedded memories within an integrated circuit. Each of the embedded memories include particular read and write protocols. The method includes providing a memory built in self test sequencer module and providing satellite engine module coupled to the memory built in self test sequencer module, to the plurality of embedded memories and applying read and write protocols to the plurality of embedded memories based upon the particular read and write protocols of each of the embedded memories. The satellite engine module includes an instruction buffer and a sequence generation engine.

Abstract: A system for a distributed computing network for managing instrumentation information from a plurality of network-connected managed entities. One or more instrumentation processes are coupled to each of the network-connected managed entities and configured to gather performance metric values. A first classification process is responsive to information describing a type of input/output operation being performed and is configured to select one or more counters based upon the type of input/output operation being performed. A second classification process is coupled to receive a performance metric value from the one or more instrumentation processes. The second classification process is responsive to a computed logarithm of a measured value of at least one metric to select and increment a particular counter of the one or more counters selected by the first classification process.

Abstract: One embodiment of the present invention provides a system that dynamically adjusts the aggressiveness of an execute-ahead processor. If a data-dependent stall condition is encountered during program execution, the system enters an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and other non-deferred instructions are executed in program order. If a non-data-dependent stall condition is encountered during execute-ahead mode, the system enters a scout mode, wherein instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the execute-ahead processor. On the other hand, if an unresolved data dependency is resolved during the execute-ahead mode, enters a deferred mode and executes deferred instructions. During this deferred mode, if some instructions are deferred again, the system determines whether to resume execution in the execute-ahead mode.

Abstract: At an ingress point to a shared transaction infrastructure, for example a shared PCI Express infrastructure, an entry in a segment table maps an address in a transaction packet to a target for the transaction packet. The entry in the segment table identifies one of a plurality of channel descriptors providing one or more of forwarding information for the transaction packet and information for constructing an additional header for the transaction packet.