Abstract: Prefetch information is generated for multi-block indirect memory access chains. A method may include selecting a chain of indirect memory accesses of a procedure, the chain comprising a head access that does not depend for its address on another prefetch candidate memory access within the procedure and an indirect access that depends for its address on the head access. The method may further include determining a prefetch-ahead value for the chain, and generating a load operation corresponding to the head access that specifies a target memory address that is dependent upon the prefetch-ahead value and an address of the head access. The method may further include, for a terminal indirect access of the chain, generating a respective prefetch operation that is dependent for its address computation on results of preceding load operations in the same manner as its corresponding terminal indirect access depends upon preceding accesses in the chain.

Abstract: A method comprises associating a plurality of locks with a data object accessed concurrently by a plurality of threads, where each lock corresponds to a respective partition of the object. The method includes using a first non-blocking transaction (such as a Hardware Transactional-Memory (HTM) transaction) to attempt to complete a programmer-specified transaction. The first non-blocking transaction may access one or more of the locks but may not actually acquire any of the locks. In response to an indication that the first non-blocking transaction failed to complete, the method may include acquiring a set of locks in another non-blocking transaction, where the set of locks corresponds to a set of partitions expected to be accessed in the programmer-specified transaction. If the set of locks is acquired, the method may include performing the memory access operations of the programmer-specified transaction, and releasing the set of locks.

Abstract: A method for managing a service executing in a zone environment involves receiving a service management request, identifying a collection of requirements required by the service management request, triggering a data collector to collect zone-specific performance attributes from a plurality of zones in the zone environment, identifying at least one zone in the plurality of zones that has zone-specific performance attributes conforming to the collection of requirements, and provisioning the service on the at least one zone based on the service management request.

Abstract: A method for monitoring performance of a mobile device involves intercepting a first monitoring request from a monitoring management host, where the first monitoring request is associated with the mobile device, enabling a monitoring agent associated with the mobile device, establishing a thin listener associated with the monitoring agent, transmitting a second monitoring request, in response to the first monitoring request, to the mobile device, receiving, by the thin listener, data from the mobile device in response to the second monitoring request, analyzing the data received in response to the second monitoring request to obtain an analysis report, and transmitting the analysis report to the monitoring management host, in response to the first monitoring request.

Abstract: A computer system may employ a first memory virtualization and corresponding virtual-to-physical address translation technique for a first application executing on a processor and a second memory virtualization and corresponding virtual-to-physical address translation technique for a second application executing on the same processor transparent to the first application. Different virtualization and corresponding translation techniques may be employed on a per-thread basis, rather than a per-application basis. Different virtualization and corresponding translation techniques may be employed for accesses to different ranges of virtual or corresponding physical addresses. Different virtualization and corresponding translation techniques may employ different page sizes. A first or second virtualization and corresponding translation technique may include page-based, segment-based, or function-based virtual-to-physical address translation.

Abstract: A computer system employing memory virtualization may employ a function-based technique for virtual-to-physical address translation. A function-based translation technique may involve replacing a generic trap handler and one or more translation table look-ups with a function to compute a corresponding physical address from a given virtual address. The computer system may be configured to determine a translation function dependent on mappings in one or more translation tables. The computer system may be configured to reorganize a memory, to reorganize one or more translation tables, or to allocate different blocks of memory to an application prior to determining a translation function. Different applications or threads executing on the computer system may employ different translation functions. Different regions of memory may be accessed using different translation functions. Some virtual addresses may be translated using a function while others may be translated using one or more translation table look-ups.

Abstract: A computer system may be configured to dynamically select a memory virtualization and corresponding virtual-to-physical address translation technique during execution of an application and to dynamically employ the selected technique in place of a current technique without re-initializing the application. The computer system may be configured to determine that a current address translation technique incurs a high overhead for the application's current workload and may be configured to select a different technique dependent on various performance criteria and/or a user policy. Dynamically employing the selected technique may include reorganizing a memory, reorganizing a translation table, allocating a different block of memory to the application, changing a page or segment size, or moving to or from a page-based, segment-based, or function-based address translation technique.

Abstract: One embodiment of the present invention provides a system that selectively monitors load instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a load instruction during transactional execution of a block of instructions, the system determines whether the load instruction is a monitored load instruction or an unmonitored load instruction. If the load instruction is a monitored load instruction, the system performs the load operation, and load-marks a cache line associated with the load instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the load instruction is an unmonitored load instruction, the system performs the load operation without load-marking the cache line.

Abstract: An infrastructure is provided for creating applications for mobile information devices, using a tag-based markup language. Developers can use the markup language to define applications and content based on easily manipulated textual tags, rather than having to write specific source code. A compiler, processes the tags in several phases. In one phase, a hierarchical object model of the application is populated with objects. Then, in another phase, a generator traverses the object model hierarchy in a top-down manner, producing source code files corresponding to objects in the object model. The code files may include various elements, for example screens, forms, and servlets. For each element required to be generated, an appropriately configured generator class is invoked. The output code can be Java source code.

Abstract: A method for tracing an instrumented program using a thread, including transferring control of the instrumented program to a trap handler to obtain an original instruction associated with a probe, loading the original instruction into a scratch space, setting a program counter to point to the scratch space, setting a next program counter to point to a next instruction, and executing the original instruction in the scratch space using the thread, wherein executing the original instruction results in placing the instrumented program in a state equivalent to natively executing the original instruction.

Abstract: A method and system thereof for supporting multiple versions of software, such as software organized as components or objects. In one embodiment, a software component (e.g., a new object) is implemented on a server node. A translator is created on the server node. The translator provides an interface to the new object for an invocation request associated with a different version of the object (e.g., an older version of the object). The new object is referenced by one identifier, and the translator is referenced by another identifier. In essence, the translator provides a form of version transparency.

Abstract: A method for storing data, that includes receiving a request to store data in a storage pool, queuing the request in an Input/Output (I/O) queue, and issuing the request from the I/O queue upon receipt of a completion interrupt from the storage pool.

Abstract: A method for tracing an instrumented program, including triggering a probe in the instrumented program, obtaining an original instruction associated with the probe, loading the original instruction into a scratch space, and executing the original instruction in the scratch space using the thread, wherein executing the original instruction results in placing the instrumented program in a state equivalent to natively executing the original instruction.

Abstract: A flange for a tape roller has a curved shape that substantially solves the problems with skewed tape while maintaining manufacturability. The tape edge makes contact with the tape flange where the slope of the curve shape is substantially flat. From the contact point of the tape and the flange, the flange shape gently curves away. The shape of the flange allows some degree of skew in the tape so that contact with the flange edge is avoided, and yet the distance between the two flanges of the roller is more easily controlled than with a roller having tapered edge flanges.

Abstract: An instruction decoder allows the folding away of JAVA virtual machine instructions pushing an operand onto the top of a stack merely as a precursor to a second JAVA virtual machine instruction which operates on the top of stack operand. Such an instruction decoder identifies foldable instruction sequences and supplies an execution unit with a single equivalent folded operation thereby reducing processing cycles otherwise required for execution of multiple operations corresponding to the multiple instructions of the folded instruction sequence. Instruction decoder embodiments described herein provide for folding of two, three, four, or more instruction folding. For example, in one instruction decoder embodiment described herein, two load instructions and a store instruction can be folded into execution of operation corresponding to an instruction appearing therebetween in the instruction sequence.

Abstract: A computer readable medium includes executable instructions for visually representing a status of a plurality of storage device slots and a plurality of attached storage devices by, and a method for visually representing a status of a plurality of storage device slots and a plurality of attached storage devices includes, assigning a logical name to a storage device slot based on an enumeration rule; detecting a storage device attached to a computer system; storing a correlation between a physical location of the storage device slot and the assigned logical name; monitoring an availability and an operating status of the plurality of storage device slots and the plurality of attached storage devices; and generating a what-you-see-is-what-you-get (WYSIWYG) representation of the plurality of storage device slots and the plurality of attached storage devices, wherein the WYSIWYG representation includes physical location information, operating status information, and logical names for the plurality of storage devic

Abstract: A method of tuning a test trace that is capacitively coupled to a number of signal traces. A method for determining a configuration of a device comprising signal traces and a capacitively coupled test trace may include selecting a test frequency of a test signal to be driven on selected signal traces during a test mode of device operation, and tuning circuit characteristics of the test trace to generate a bandpass frequency response including a passband and a stopband, where a detection frequency corresponding either to the test frequency or a selected harmonic of the test frequency is included in the passband. Tuning of circuit characteristics may include selecting a degree of capacitive coupling between the test trace and the signal traces such that, within a specified constraint for signal degradation on the signal traces, the bandpass frequency response of the given test trace satisfies a specified transmission requirement at the detection frequency.

Abstract: A garbage collector that reclaims memory for a mutator does so space-incrementally, employing remembered sets associated with respective heap regions to keep track of where the mutator has notified it of writing references into the associated regions. The collector reserves some heap regions for objects that it has found to be “popular,” i.e., to which it has observed a large number of references. When the mutator writes such a reference, it refrains from making the kind of notification to which the garbage collector would otherwise respond by updating a remembered set. Although this deprives the garbage collector of the ability to maintain complete remembered sets for popular-object regions, those regions usually have no unreachable objects or very few, so the collector can dispense with collecting them or can collect them less frequently, in a way that does not rely on remembered sets.

Abstract: A registry service is described which uses a partitioned publisher assertion recording and accessing scheme. A publisher assertion regarding a relationship between entities (e.g., business or other types of entities) is encoded within a directory information tree in a memory. The publisher assertion includes publisher assertion part nodes corresponding to entity nodes in the directory information tree. The publisher assertion is complete if all publisher assertion parts corresponding to entities in the relationship are present in the directory information tree. The service may include a network including directory servers and registry servers. The publisher assertions are manipulated by authorized publishers and accessed by users using a variety of techniques, the operations of which are performed by such parties and/or are encoded upon computer-readable media.

Abstract: A package for an integrated circuit (IC) die comprises a substrate and a lid. The substrate has an upper surface facing an interior of the package and a lower surface facing an exterior of the package. The upper surface of the substrate carries an IC die and provides electrical connections from the IC die to the lower surface of the substrate. The lid includes an outer lid and an inner lid. The inner lid is positioned over the IC die and is in thermal communication with the IC die. The inner lid is formed of a material suitable for conducting heat away from the IC die. The outer lid is attached to the upper surface of the substrate. A gap extends between the outer lid and inner lid.