Abstract: A technique for detecting changes in a signal that is measured and reported by quantization uses a model that is updated in response to the sampling of quantized values representing the signal. In one stage, (i) frequencies of occurrences of different sampled quantized values in the stage are calculated and (ii) mean frequencies for each of the different sampled quantized values in the stage are calculated and recorded. In a next stage, frequencies of occurrences of different sampled quantized values occurring after an end of the preceding stage are calculated and statistically compared with the mean frequencies of the different sampled quantized values determined in the preceding stage. Dependent on this comparison, a notification may be issued indicating the signal is anomalously changing.

Abstract: One embodiment of the present invention provides a system that enhances reliability, availability and serviceability in a computer system by replacing a signal from a failed sensor with an estimated signal derived from correlations with other instrumentation signals in the computer system. During operation, the system determines whether a sensor has failed in the computer system while the computer system is operating. If so, the system uses an estimated signal for the failed sensor in place of the actual signal from the failed sensor during subsequent operation of the computer system, wherein the estimated signal is derived from correlations with other instrumentation signals in the computer system. This allows the computer system to continue operating without the failed sensor.

Abstract: One embodiment of the present invention provides a system that logically partitions different classes of translation lookaside buffer (TLB) entries within a single caching structure. Upon receiving a request to lookup an address translation, the system applies a hash function to parameters associated with the request to determine a corresponding location in the single caching structure where a TLB entry for the request can reside. If the corresponding location contains a TLB entry for the request, the system returns data from the TLB entry to facilitate the address translation. This hash function partitions the single caching structure so that different classes of TLB entries are mapped to separate partitions of the single caching structure. In this way, the single caching structure can accommodate different classes of TLB entries at the same time.

Abstract: One embodiment of the present invention provides a system that dynamically configures selected methods for instrument-based profiling at run-time. The system operates by identifying a root method in a target application, wherein methods that are reachable from the root method during execution of the target application are to be instrumented. Upon loading of a new method during execution of the target application, the system identifies methods in the target application that become reachable from the root method through the new method. The system then instruments methods that are reachable, loaded and have not been instrumented before.

Abstract: A method for detecting transfer errors in an address bus is provided. In this method, a first address parity is generated using a memory address. Next, at least two data error-correction-code (ECC) check bits are scrambled using the first address parity. Subsequently, the data ECC check bits are written to a memory and the data ECC check bits enable detection of transfer errors in the address bus. A system for detecting transfer errors in an address bus is also described.

Abstract: In one embodiment, a node for a multi-node computer system comprises a coherence directory configured to store coherence states for coherence units in a local memory of the node and a coherence controller configured to receive a coherence request for a requested coherence unit. The requested coherence unit is included in a memory region that includes at least two coherence units, and the coherence controller is configured to read coherence states corresponding to two or more coherence units from the coherence directory responsive to the coherence request. The two or more coherence units are included in a previously-accessed memory region, and the coherence controller is configured to provide the requested coherence unit with a predicted coherence state responsive to the coherence states in the previously accessed memory region.

Abstract: Users can browse a repository of search results obtained from a search engine by mounting a virtual file system, for example, on a network server over a network. The virtual file system contains a hierarchy of categories and is associated with a document repository. Consequently, although documents could be located anywhere, documents indexed by the virtual file system are accessed by users in the original document locations. Accordingly, all changes made by a user are made to the original document rather than to a copy of the document. Therefore, there is no need to upload a copy of the document to the original file location. The search engine can be associated with the virtual file system so that the search engine recognizes the changed document immediately.

Abstract: A method for using dependency-based grouping to establish class identity comprises categorizing a plurality of classes into a set of class groups based at least in part on one or more dependencies between the classes, and generating metadata to be use for loading the classes, where the metadata includes a mapping between the set of class groups and the plurality of classes. The metadata may also include respective signatures for class groups and/or the individual classes. The method may also include validating, using at least a portion of the metadata, the identity of a particular version of a class of the plurality of classes, prior to loading the version for execution.

Abstract: In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

Abstract: A verification mechanism monitors incoming and outgoing traffic between a channel adapter and a switch fabric in an InfiniBandSM system in order to verify that the InfiniBandSM protocol is correctly followed by the channel adapter. The verification mechanism uses a simple hardware-independent interface to query the channel adapter hardware for specific values and completion queue, queue pair and work queue element attributes that are required for verification. The verification mechanism creates a plurality of verification components that monitor incoming and outgoing messages and verify that each of the channel adapter elements correctly follows the protocol. The verification mechanism is controlled by a verification application programming interface (API) that allows different test benches and tests to incorporate InfiniBandSM protocol verification in any test system for use with any hardware.

Abstract: A server blade is provided which comprises a processor. The server blade additionally comprises an enclosure which encloses the processor. The server blade is configured as a field replaceable unit removably receivable in a carrier of a modular computer system, and is configured as an oversized unit to span more than one standard information processing module receiving location in the carrier.

Abstract: A storage area network (SAN) system that includes a self-contained storage system is managed by a three-tier management system. Management of the self-contained storage system and data services for that system is provided by a three-tiered dedicated management system mirroring the management system that manages the SAN system. In both the SAN management system and the dedicated management system the lowest, or agent, tier comprises Common Information Model (CIM) provider objects that can configure and control the internal components, including the internal switch fabric and disks of both systems. The middle, or logic, tier of the dedicated management system is a set of management facades and federated Java beans. In order to integrate the dedicated management system with the SAN management system, the beans comprising the middle tier of the dedicated management system are also deployed in a shared Jiro™ station associated with the SAN management system.

Abstract: Application code maintenance often imposes rebuilding and/or a patch kit update from a source code vendor. Users of such applications often find such conventional rebuilds and install efforts intrusive. An extensible object-relational (O-R) model operable for dynamic additions to an existing baseline of modeled data specifications mitigates interim patches and builds by employing a scripted modeling form and a corresponding relational form. The scripted modeling form, such as an XML file, is readily modifiable from existing data specifications, such as those driven by a recognized standard, while the relational form is seamlessly updated within an existing application environment without requiring rebuilding or patch kits to implement. The extensible O-R model defines data characteristics of data specifications, and the relational model is updated by instantiating an object or entry into the modeled relational specifications based on the extensible O-R model.

Abstract: A circuit board including a signal transmission channel includes a dielectric substrate and a signal transmission channel which may be formed on the dielectric substrate. The signal transmission channel may include a conductor, a lossy dielectric material which may longitudinally encapsulate the conductor and a conductive material which may longitudinally encapsulate the lossy dielectric.

Abstract: One embodiment of the present invention provides a system that approximates a shape of an object with a closed Bezier curve. During operation, the system receives a specification for the shape of the object. The system also produces an objective function for the area of a closed Bezier curve, wherein the objective function expresses the area of the closed Bezier curve as a function of the locations of control points that define the closed Bezier curve. Next, the system uses the specification for the shape of the object to generate exterior constraints for the closed Bezier curve, wherein the exterior constraints ensure that the closed Bezier curve remains on the exterior of the object. Finally, the system minimizes the area of the closed Bezier curve subject to the exterior constraints to produce a minimum-area closed Bezier curve on the exterior of the object which encloses the shape of the object.

Abstract: A direct contact cooling liquid embedded package design for use with a computer central processor unit is suitable for thermal management of high heat dissipation electronic components such as server processors. The direct contact cooling liquid embedded packaged CPU has mechanical coupling and embedded plumbing that attaches to the board pumped liquid supply and direct contact cooling liquid of the heat-generating portion of the CPU. A direct contact cooling liquid embedded packaged CPU removes higher levels of heat directly from the core of the processors by convective cooling. Cooling liquid is introduced into the package of the server CPU by mechanically attaching the CPU to the board through a socket interconnect. Pins of the socket serve to provide electrical connection between the board and the CPU, while a few pins are designed for the purpose of inlet and outletting cooling liquid into and out of the CPU package.

Abstract: One embodiment of the present invention provides a system that provides virtual transport layer security on a virtual network to facilitate peer-to-peer communications. The system creates a first pipe that functions as a one-way input channel into a first peer. Next, the system associates a first peer identifier with the first pipe and advertises the availability of this first pipe. A second peer connects to this first pipe to communicate with the first peer. The system also creates a second pipe at the second peer, and a second peer identifier is associated with this second pipe. The first peer connects to this second pipe to communicate with the second peer. The first pipe and the second pipe form a virtual connection through which the first peer and the second peer can communicate securely.

Abstract: A system and method for reusing an R_Key associated with InfiniBand virtual address space mapped to local, host, storage. An R_Key is initially assigned by an HCA (Host Channel Adapter) when a host registers a set of local storage buffers. The HCA maps the local buffers to virtual address space and returns the R_Key. When the host augments the mapped local storage by identifying additional buffers, the HCA maps the larger storage area to virtual address space and returns the same R_Key. When the host removes local storage from the mapping scheme, the HCA returns a smaller virtual address space associated with the same R_Key.

Abstract: A multi-threaded accept in a vertical perimeter communication environment is disclosed. Embodiments of the present invention include a method for processing a connection in a multi-processor server system comprising receiving a connection indicator packet on a listener of the server system wherein the connection indicator packet is associated with a connection to be established. In response to the connection indicator, generating a connection data structure defining a connection path for the connection and assigning the path to a processor of the multi processor server. The path transmits a first acknowledgement packet in response to the connection indicator wherein the listener is free to process subsequent packets. The path receives a second acknowledgement packet to establish the connection on the processor and the path processes a plurality of data packets on the processor associated with the connection, wherein the data packets are identified with the path based on the data structure.

Abstract: An apparatus and method for mapping memory addresses to reduce or avoid conflicting memory accesses in memory systems such as cache memories is described in connection with a multithreaded multiprocessor chip. A CMT processor reduces the probability of hot-spots in cache operations by hashing certain bits of a physical cache address to form a hashed cache address. By using exclusive OR functionality to hash the index bits, an efficient address transformation is achieved for indexing into an L2 cache memory.