Abstract: An invention is provided for creating a test summary report. A test application is executed on a platform, where the test application is executed using a status utility having functions that generates XML code. The test results are generated in a XML enabled format using the status utility, and are output to a test execution log file. The test execution log file is processed to generate a well-formed XML test reports file, which is then logically arranged to create a logically arranged XML test reports file. The logically arranged XML test reports file is converted into a HTML test summary report.

Abstract: A large multimaster I2C bus system is partitioned into smaller bus segments. The bus segments are connected by bridges that isolate the segments and direct selected transactions and commands between the segments. The bridge may handle bus segment error conditions and particularly a hang on the Port B bus by attempting to cause any device on the bus segment to respond after the bus bridge has attempted to acquire the segment for a first predetermined period of time. If the bus responds within the first predetermined period of time, the bus bridge resets the bus segment.

Abstract: Techniques for modeling a circuit cell of a microprocessor or other integrated circuit for hierarchical powergrid analysis are disclosed herein. Distribution coefficients, used to distribute node voltages and capacitances to respective parts of the cell, are determined for each internal node of the cell. Current distribution coefficients may also be determined for each resistor in the cell. Using the distribution coefficients, internal cell capacitances are modeled as port capacitors. Resistive elements are modeled as a resistor network having no internal nodes. Transistor elements are modeled as port current sources. Such a model permits back calculation of internal node voltages and currents.

Abstract: An input/output interface is used to transmit data between a transmitting circuit and a receiving circuit. Selectively during both system startup and system operation, a known bit pattern transmitted by the transmitting circuit is compared to a received bit pattern. The received bit pattern may be seen at the receiving circuit or a voltage regulator that is used to control the power supply level of the input/output interface. Dependent on the comparison of the known bit pattern and the received bit pattern, a bit error rate across the input/output interface is determined, in response to which the voltage regulator adjusts the power supply level of the input/output interface.

Abstract: Processing circuitry is integrated within a hardware security module (HSM) chip card. The processing circuitry is configured to operate in accordance with a set of program instructions stored in a memory integrated within the HSM chip card. The set of program instructions includes program instructions for implementing a public-key cryptography standard (PKCS). The PKCS includes processes for generating and storing a master key. The master key is to be stored in the memory integrated within the HSM chip card. Also, using the master key stored in the memory of the HSM chip card, the HSM chip card enables direct management control of standard chip cards.

Abstract: Access to external service providers is provided through portlets, where each portlet accessible by a user is represented on the display of the user device. Through use of a dynamic content channel, e.g., a portlet, a highly customizable content page may be produced for any individual client system. When a portlet is selected on a user device, the content associated with the portlet is retrieved and automatically transformed into data that can be displayed by that user device. Thus, a particular user device is not limited to accessing content in a format identical to that associated with the user interface in use on the user device. Consequently, the user's ability to access a wide variety of content sources independent of the characteristics of the particular user device is further enhanced.

Abstract: There is provided a drive carrier. The drive carrier is configured to receive a media drive and is also configured to be removably receivable in a receiving location of a computer system. The drive carrier includes a base portion, a handle portion and a latch mechanism for securing the carrier within the receiving location. The base portion and the handle portion are configured to co-operate to operate the latch mechanism on insertion and/or removal of the carrier from the receiving location, for inserting and/or removing the carrier from the receiving location and operating the latch mechanism with a single movement of the handle portion.

Abstract: A hardware implemented method for writing data to a cache is provided. In this hardware implemented method, a Block Initializing Store (BIS) instruction is received to write the data from a processor core to a memory block. The BIS instruction includes the data from the processor core. Thereafter, a dummy read request is sent to a memory controller and known data is received from the memory controller without accessing a main memory. The known data is then written to the cache and, after the known data is written, the data from the processor core is written to the cache. A system and processor for writing data to the cache also are described.

Abstract: A method and apparatus for performing on-chip voltage sampling of a weakly-driven node of a semiconductor device are disclosed. In some embodiments, the node is a floating node or is capacitively-driven. In some embodiments, it is involved in proximity-based communication. Sampling the node may include isolating the signal to be sampled using a source-follower amplifier before passing it to the sampling circuit. Sampling the node may include biasing the node to a desired voltage using a leaky transistor or other biasing circuit. In some embodiments, the biasing circuit may also be used to calibrate the sampler by coupling one or more calibration voltages to the node in place of a biasing voltage and measuring the sampler output. The sampler may be suitable for sub-sampling high frequency signals to produce a time-expanded, lower frequency version of the signals. The output of the sampler may be a current communicated off-chip for testing.

Abstract: One embodiment of the present invention provides a system that systematically monitors and records performance information in a computer system. During operation, the system periodically measures a number of performance parameters in the computer system. The system then stores data representing values for the measured performance parameters in a long-term storage space. Next, the system recurrently compresses data stored in the long-term storage space, thereby allowing additional data representing newly collected performance information to be stored in the long-term storage space.

Abstract: A user is provided with the choice of selecting either a client or a server for providing either local or remote services on a data file, respectively, if both the server and the client have the resources for the desired service. The user may select the client or the server upon requesting a particular operation or service on a data file or may enter pre-selections according to which of the client or the server will be selected for execution of the operation. A client program and a server program for providing the service may be divided into at least two modules and the client and server may be selected for executing the first and second modules.

Abstract: A device configured to recover and repeat source synchronous data. The device is configured to receive source synchronous data via a first interface and recover the received data utilizing a first clock signal which is generated to be approximately ninety degrees out of phase with the received clock signal. A second clock signal is generated to be in phase with the received source synchronous clock signal. The second clock signal is the utilized to select a newly generated clock signal and latched data for transmission in a source synchronous manner. The device is further configured to shift the phase of the generated first clock signal to be approximately ninety degrees out of phase with the received data signal.

Abstract: A method for installing an image on a client including obtaining a wanboot binary from the boot server, determining whether the wanboot binary is valid, obtaining a security payload from the boot server using the wanboot binary if the wanboot binary is valid, establishing a first secure connection between the client and boot server, obtaining a boot file system from the boot server using the first secure connection, installing the boot file system on the client to obtain a kernel, establishing a second secure connection between the client and an installation server using the security payload and the kernel, obtaining an installation image from the installation server using the kernel and the second secure connection, and installing the installation image on the client.

Abstract: A method for tracing on a processor including executing an executing control block on the processor to obtain data, wherein an interrupt on the processor is disabled prior to executing the execution control block and the interrupt is enabling after execution of the execution control block is completed, storing the data in a first buffer, wherein the first buffer is set to active, and setting the first buffer to inactive and setting a second buffer to active, wherein the interrupt on the processor is disabled prior to switching the first buffer to inactive and the interrupt is enabling after setting the second buffer to active.

Abstract: A method for correcting an error in a first block including detecting an error in the first block, generating a first permutation of the first block, calculating a first permutation checksum for the first permutation of the first block, and replacing the first block with the first permutation of the first block, if a first block checksum matches the first permutation checksum.

Abstract: A programmer to set his own input error handler after examining the context where the error occurs by utilizing a set error handler subroutine. The context may be provided by the system library to the user's handler routine so it can make a better judgment on how to proceed next. The customizable nature of the invention allows programmers to suit the error handling to individual application needs.

Abstract: A system and method for controlling access to data in a distributed computer system. Distributed Token Manager (DTM) is a system-level service that coordinates read/write access of data objects (tokens) in a multi-process and multi-threaded environment. The DTM may support a transactional model such that write operations to a data object performed by a client process or thread can be either committed or rolled back.

Abstract: Committing data loaded on a device includes computing a program unit storage commitment fingerprint over a program unit if the program unit is finally loaded in a non-volatile memory on the device, associating the program unit storage commitment fingerprint with the program unit and storing the program unit storage commitment fingerprint.

Abstract: A system and method for authenticating a legacy service using internet technology is disclosed. An authentication module is associated with the legacy server. Service requests from a user of the legacy server are passed to the authentication module. The authentication module generates a service request for a web server, requesting access to a protected page from the web server, and transmits the user's credentials to the web server. The web server attempts to access the protected server, which causes the web server to access a network-based authentication service to determine whether the user's credentials qualify for access to the protected page. The web server transmits a message back to the authentication module, which determines whether the user's credentials qualify for access the legacy server based on the message from the web server.