Abstract: The present invention provides for token based signing of an unsigned binary which may be a stream of bits (e.g., 0's and 1's). The unsigned binary is signed using a secret key which resides in a token (e.g., a smart card), which makes the secret key available to the token holder. The unsigned binary is downloaded and verified for authenticity by the token coupled to a computing device. In one embodiment, the downloaded unsigned binary is encrypted. If the unsigned binary is authentic, it may be used to replace the prior firmware on that computing device.

Abstract: Verification of a software program may be automated by receiving a program source file comprising program source code and at least one formal specification annotation, extracting the at least one formal specification annotation from the program source file, compiling the program source code and linking the compiled program and the at least one extracted formal specification annotation to create an executable program that includes at least one reference to an executable formal specification module. According to one aspect, a virtual machine includes a target virtual machine for executing one or more program implementation instructions, and a formal virtual machine for executing one or more formal specification modules corresponding to one or more program implementation instructions and configured to call a formal specification module, and to compare a first result obtained by executing the program implementation instructions with a second result obtained by the call to the formal specification module.

Abstract: A method for maintaining patch information for a plurality of clients using a remote file system that includes obtaining component information from a report associated with each of the plurality of clients, populating a patch file on the remote file system when a component found on the plurality of clients is not current based on component information, and accessing the patch file on the remote file system to update the plurality of clients, wherein the report and the patch file are stored in the remote file system.

Abstract: A method and system for trace generation using memory index hashing. A method may include generating an extended trace representative of M threads of instruction execution from a trace representative of N threads of instruction execution, where N and M are integers, N?1 and M>N, and where each of the N threads of the trace includes memory references to respective memory addresses. Generating the extended trace from the trace may include replicating the N threads to generate the M threads, assigning a respective identifier to each of the M threads, and for a given one of the M threads, hashing a first portion of each of the respective addresses dependent upon the respective identifier of the given thread, where the first portion of each of the respective addresses corresponds to at least part of an index of a memory structure shared by at least two of the M threads.

Abstract: A system for testing a synchronous link utilizing a single test pattern sequence. Components coupled via a link are each configured to generate and check test patterns according to a single repeated test pattern sequence. Test patterns which are generated are based upon two simple patterns. Each test cycle, a bit is chosen from one of the two patterns for use in generating the test pattern. A sixteen cycle test pattern sequence is utilized in which values are chosen from one or the other of the two patterns in a predetermined manner. In a bi-directional test, two components which are coupled via a link alternate driving selected values based upon the predetermined sequence. Each component may alternate driving sequences of one or more cycles. An ordering of cycles may be chosen to test various permutations of driver interaction between the respective components.

Abstract: Disclosed are novel methods and apparatus for persistent queuing in distributed file systems. In an embodiment, an apparatus is disclosed. The apparatus includes a distributed file system including a plurality of remote systems. The plurality of remote systems includes a sender site and a receiver site. The apparatus further includes a local queue accessible by the sender site; a remote queue accessible by the receiver site; a next attempt time indicator; and an attempt counter. The next attempt time indicator may specify a next time to install a transferred file on the receiver site. The attempt counter indicates how many attempts have been made to install the transferred file on the receiver site.

Abstract: A method for arbitrating channel bandwidth among a plurality of logical connections desiring access over a communication channel to transmit data is provided. The method includes detecting a connection desiring access through the communication channel and assigning the connection to a group having arbitration parameters. Then, the method packetizes the data to be transmitted and transmits each packet of the data in time slices. In each time slice, data is transmitted using the arbitration parameters of the group.

Abstract: The present invention defines a mechanism for automatic synchronization of scripting variables in an action tag extension facility. Attached to each action, there is a TagExtraInfo class that describes the action. The TagExtraInfo class knows the attributes of the class, including the names of the scripting variables introduced or modified by the action. At translation time, a tag handler accesses the information from the TagExtraInfo class for each tag in a page. At run time, a pageContext object is created containing a mapping of scripting variables to values. The values are visible to the scripting code, and the scripting code can modify the values. Also, the values are accessible by the action code. The action code can modify the values or create new values and assign the values to scripting variables so that the scripting code can modify them later. Thus, the present invention allows action tags to be created without explicit knowledge of the scripting language used to create a page.

Abstract: One embodiment of the present invention provides a processor which selectively fetches cache lines for store instructions during speculative-execution. During normal execution, the processor issues instructions for execution in program order. Upon encountering an instruction which generates a launch condition, the processor performs a checkpoint and begins the execution of instructions in a speculative-execution mode. Upon encountering a store instruction during the speculative-execution mode, the processor checks an L1 data cache for a matching cache line and checks a store buffer for a store to a matching cache line. If a matching cache line is already present in the L1 data cache or if the store to a matching cache line is already present in the store buffer, the processor suppresses generation of the fetch for the cache line. Otherwise, the processor generates a fetch for the cache line.

Abstract: An adaptive subgridding method for power/ground plane simulations. The method includes superimposing a grid of cells onto a circuit plane. For each cell, the method may determine a fill ratio representing the amount of area in a given cell that overlaps with the circuit plane. For each cell having a fill ratio that is less than a predetermined upper limit or a predetermined lower limit the cell may be divided into a plurality of subcells. The method may then determine the fill ratio for each of the subcells. As with the original cells, each of the subcells having a fill ratio less than the predetermined upper limit and greater than the predetermined lower limit may be further subdivided into additional subcells. The loop may repeat itself until a predetermined integer value is reached, wherein the integer value indicates the number of times a cell may be subdivided.

Abstract: Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue.

Abstract: Location-independent references include a live reference containing a location of a remote object and a universally unique identifier (UUID) which provides a unique global reference to that remote object. If a method call to the remote object using the live reference fails, the UUID is used to obtain a new reference to the remote object and the new reference is then used to make another method call. A new reference can be obtained from an identifier directory that contains a mapping between UUIDs and location-independent references. When a remote object is first created, or when a remote object is moved from one location to another, the remote object registers with any and all such directories that it can find in its environment. These registrations are leased; that is, if they are not occasionally refreshed by the remote object which registered them, they are dropped from the directory.

Abstract: A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The technique maintains the working register file entry until at least a predetermined number of subsequent instructions have similarly proceeded through the particular stage.

Abstract: A system for binary code instrumentation to reduce effective memory latency comprises a processor and memory coupled to the processor. The memory comprises program instructions executable by the processor to implement . a code analyzer configured to analyze an instruction stream of compiled code executable at an execution engine to identify, for a given memory reference instruction in the stream that references data at a memory address calculated during an execution of the instruction stream, an earliest point in time during the execution at which sufficient data is available at the execution engine to calculate the memory address. The code analyzer generates an indication of whether the given memory reference instruction is suitable for a prefetch operation based on a difference in time between the earliest point in time and a time at which the given memory reference instruction is executed during the execution.

Abstract: In a data storage system, content-containing objects to be stored are added to a storage hierarchy that is based on content relationships. The content of each stored object is encrypted and a stub is associated with that object. For each stored object other than a root object, the stub comprises a function of a decryption key for the content of that object and the stubs of all of the ancestors of that object. The stubs can be used to calculate a new stub for a data object to be inserted into the storage hierarchy and to generate a decryption key for an existing object. Since these latter calculations for an object involve the stubs of all ancestors of that object, deleting a stub for an object securely deletes that object and all its descendants. An object can be moved by recalculating its stub.

Abstract: Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a configurable predecode mechanism can be employed to select, for respective instruction patterns, between fixed decode and programmable decode paths provided by a processor. In this way, a patchable and/or programmable decode mechanism can be efficiently provided. In some realizations, either (or both) predecode or (and) decode may be configured or reconfigured post-manufacture. In some realizations, either (or both) predecode or (and) decode may be configured at (or about) initialization. In some realizations, either (or both) predecode or (and) decode may be configured at run-time.

Abstract: Architectural techniques and implementations that defer enforcement of certain delayed control transfer instruction (DCTI) sequencing constraints or conventions to later stages of an execution pipeline are described. In this way, complexity of a processor pipeline front-end (including fetch sequencing) can be simplified, at least in-part, by fetching instructions generally without regard to such constraints or conventions. Instead, enforcement of such sequencing constraints and/or conventions may be deferred to one or more pipeline stages associated with commitment or retirement of instructions. Higher fetch bandwidth may be achieved in some realizations when, for example, DCTI couples are encountered in an execution sequence.

Abstract: Methods and systems are provided for adapting software applications for download and execution on a variety of different mobile devices which employ different Application Execution Environments. An Application Download Protocol for transferring applications to mobile devices is also provided. Mobile devices can be matched with compatible applications according to functionality required by the applications and functionality provided by the mobile devices. Applications submitted by developers can be automatically matched to application categories, thus facilitating user selection of applications. Data used by applications running on mobile devices can be remotely managed by application developers, allowing developers to remotely control the type and presentation of data on mobile devices without the need for data management servlets to be provided by the developers.

Abstract: Means and a method for authenticating a photographic image (3) on an identification device (1), the identification device (1) being provided with: a photographic image of a person (3) and a microprocessor (8), the microprocessor (8) having: a) a processor (7), b) a memory (9) connected to the processor (7) and having stored authentication data, and c) interface means (5) connected to the processor (7) for communicating with an external device, wherein said photographic image (3) comprises stegano-graphically hidden information, the content of which together with said authentication data allows authentication of said photographic image (3), the method having the following steps: a?) scanning the photographic image (3) and generating image data. b?) analyzing these image data in accordance with a predetermined image analysis procedure to derive said hidden information, and c?) carrying out the authentication of the photographic image (3) based on the hidden information and the authentication data.