Abstract: A method for prefetching data in a file system includes detecting an access to a file in the file system, wherein an instance of file access information is generated upon each access to the file, placing a plurality of the instance of file access into an access history buffer, performing a collinear check between at least three of the plurality of the instance of file access information in the history buffer to determine a sequential access pattern, creating a prefetch stream based on the sequential access pattern if the collinear check succeeds, and placing the prefetch stream into the prefetch stream buffer.

Abstract: An improved technique for power distribution for use by high speed integrated circuit devices. A mixture of high dielectric constant, Er and low Er materials are used in a dielectric layer sandwiched between the voltage and ground planes of a printed circuit board that is used to fixture one or more integrated circuit devices. The low Er material is used in an area contained by the location of the integrated circuit device and its corresponding decoupling capacitors located nearby. High Er material is used in areas between the regions of low Er material. The low Er material improves that speed at which current from an adjoining decoupling capacitor can propagate to a power pin of the integrated circuit device. The high Er material mitigates cross-coupling of noise between the low Er regions.

Abstract: A method for locating a root block in file system metadata, includes traversing the file system metadata to locate a leaf block, wherein the leaf block comprises a plurality of root blocks and at least one of the plurality of root blocks is unallocated, allocating the at least of one the plurality of unallocated root blocks to obtain an allocated root block, wherein the leaf block is associated with a fill count and the fill count is less than a maximum fill count of the leaf block.

Abstract: An inverse toggle circuit includes a pair of input connections for receiving each of four possible input signal combinations in a sequential rotational manner. Each of four data paths are defined to be exercised in accordance with a respective input signal combination. A first output connection is controlled by first and third data paths. A second output connection is controlled by second and fourth data paths. Each data path is defined such that a currently exercised data path generates an output signal having an asserted state on the output connection that is controlled by the currently exercised data path. The currently exercised data path is also defined to cause a next data path in the sequence to generate an output signal having a non-asserted state on the output connection that is controlled by the next data path.

Abstract: In one embodiment, a processor is configured to execute a window swap instruction. The processor comprises a register file (that comprises a plurality of registers) and first and second execution units coupled to the register file. A first pipeline associated with the first execution unit has a first number of pipeline stages, and a second pipeline associated with the second execution unit has a second number of pipeline stages. The first execution unit is configured to change the current register window from the first register window to the second register window in the register file in response to the instruction. The second execution unit is configured to perform an operation defined by the instruction and write the result to the register file. The second number of pipeline stages exceeds the first number, whereby the second register window is established in the register file prior to writing the result.

Abstract: A rack-mounted assembly (10) comprises one or more racks, each capable of containing one or more printed circuit boards (PCB) (18), interconnected by a backplane (15) which is located along the bottom of a shelf (14). This position of the backplane (15) allows the rear wall of the rack-mounted assembly to be perforated, thereby permitting a cooling airflow for the PCBs to pass in through the front of the assembly and then out through the back. An insertion mechanism is provided to allow a PCB to be inserted into a rack. To achieve this, the PCB must first travel backwards into the rack-mounted assembly, and then downwards into engagement with the backplane (15). In one embodiment, this is accomplished by supporting the PCB from a hanger (100) which moves in and out of the rack-mounted assembly along a guide rail (45). The hanger includes slots (115) that retain pins (110) from the PCB. The slots are orientated diagonally upwards and backwards.

Abstract: An improved circuit for sensing and programming fuses in integrated circuits. The circuit is broadly comprised of a fuse cell, a reference circuit, a sense amplifier and a level detector. In one embodiment of the present invention, a two-stage sensing scheme is implemented. The improved fuse sensing circuit uses current-mode sensing and implements an auto-read current reduction scheme. Using a level-detect circuit, the virtual ground is raised automatically if the high-voltage power supply exceeds core supply (Vdd) by a fixed dc voltage. This reduces effective sensing voltage and the read current and thus helps preserve unblown fuse integrity. In one embodiment of the invention, four modes of operation are implemented: “Normal Read,” “Unblown_Read,” “Blown_Read_1” and “Blown_Read_2.” The default read mode is the “normal read” while the “Unblown” and “Blown” read modes are for fuse calibration purposes.

Abstract: A system that characterizes degradation of a component in a system. During operation, the system monitors inferential variables associated with a specimen of the component. Next, the system determines a time for the onset of degradation for the specimen and determines a time for the completion of degradation for the specimen. The system then computes a time interval between the onset of degradation and the completion of degradation, and uses the time interval to look up an entry in a defect library to obtain information which characterizes the degradation of the specimen of the component.

Abstract: One embodiment of the present invention includes a method for enabling a client node to automatically read ahead data from a network based file system. Specifically, in response to an application operating on the client node requesting a data page, the client node requests delivery of data pages from the network based file system. Upon reception, these data pages can each be served to the application. After each data page is served, it is determined whether the number of unrequested available data pages is less than the value of M. If so, an asynchronous read-ahead request is sent to a primary node of the network based file system for P number of data pages. The values of M and P can be such that P data pages can be fetched before M data pages are consumed by the requesting application.

Abstract: A method and apparatus are provided, the method and apparatus comprising sending an output of a free-running counter to a comparator for a clock shaper logic unit, the free-running counter incremented every time a double-speed clock rises for an on-chip system and sending at least one input from a central processing unit (CPU) to the comparator for the clock shaper logic unit, the at least one input specifying a desired frequency. The method and apparatus also comprises producing a central processing unit (CPU) clock in the clock shaper logic unit based on the output of the free-running counter and the at least one input specifying the desired frequency by comparing a bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency.

Abstract: Broadly speaking, a method is provided for evaluating nets in a crosstalk noise analysis. More specifically, a method is provided for evaluating timing window overlap between a pair of nets. The method includes selecting one timing window from each net of the pair of nets for analysis. The method further includes analyzing characteristics of the timing windows selected from the pair of nets to identify a timing window overlap presence, wherein the timing window overlap presence can exist between any two timing windows associated with each net of the pair of nets, respectively.

Abstract: One or more fingerprints may be utilized in each class in order to allow for faster subtype checking. A subclass fingerprint may be utilized to track the superclasses of a class, and an interface fingerprint may be utilized to track the locally declared interfaces of the class and any interfaces which it inherits. This allows for subtype checking that is extremely fast and efficient by utilizing comparison and other logical operations during the checking.

Abstract: An interconnecting device for a data processing system. The interconnecting device comprises a first plurality of connection ports for connecting to first components of the data processing system. The interconnecting device further comprises a second plurality of connection ports for connecting to second components of the data processing system. And, a cover is affixed over the first plurality of connection ports to restrict access to the first plurality of connection ports.

Abstract: One embodiment of the present invention provides a system that avoids write-after-read (WAR) hazards while speculatively executing instructions on a processor. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint, defers the instruction, and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of unresolved data dependencies are deferred, and wherein other non-deferred instructions are executed in program order. While deferring the instruction, the system stores the instruction along with any resolved source operands for the instruction into a deferred buffer.

Abstract: A method and apparatus for clipping video information before scaling. In an embodiment of the invention, a transmitter obtains video information in the form of image data, as well as clipping information defining one or more display regions in which the image data is to be displayed. In accordance with the clipping information, the transmitter performs clipping operations on the image data, and transmits the clipped image data to a receiver. Prior to displaying the clipped image data, the receiver performs any needed scaling of the clipped image data to conform to the dimensions of the display regions. By performing clipping operations prior to transmission, and scaling operations subsequent to transmission, unnecessary image data is omitted and greater transmission efficiency is achieved.

Abstract: A method of reducing interference among applications co-located in a process when using dynamic libraries is disclosed. For each dynamic library, multiple instances of the dynamic library are loaded in the same operating system process (or process), whereas each instance of the dynamic library corresponds to one of the multiple applications co-located in the same process. In particular, the text segments (or read-only segments) of the instances of the dynamic library are mapped to the same physical memory pages, leading to a low memory footprint. Moreover, within the process, a co-located application's access to a dynamic library is directed to the instance (of the dynamic library) associated with the accessing application, reducing interference among applications co-located in the same process.

Abstract: Methods for monitoring an application running on a server are described. Method steps include maintaining counters of statistics related to operation of the application, collecting first operational statistics based on counters from one or more application components, collecting second operational statistics based on counters from one or more application runtime environment components, updating aggregation statistics based on the collected statistics, and storing the statistics for access by a presentation agent which can interface with external monitoring tools. The nature and level of the collected statistics provide valuable insight into the operation of the application of interest.

Abstract: A digital signature is embedded in the header of selected content to be transmitted. A recipient of the content identifies the priority of the content according to header line content or signature presence and segregates signed priority content from non-authenticated content. Signature generation and filtering as well as certification are accomplished by running application specific software on a selected computer. Required e-mail access level may vary with the intended recipient and/or with the instrumentality by which e-mail access is allowed.

Abstract: One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

Abstract: Broadly speaking, an apparatus for efficiently utilizing a shared packet buffer memory in a switch and a method for operating the same is provided. More specifically, the apparatus includes a memory having a number of buffers configured to be operated in a ratcheted manner. The ratcheted manner in which the memory is operated causes each incoming data stream to be distributed across the number of buffers. Each stored data stream can also be retrieved from the number of buffers for output from the memory in a similar ratcheted manner. The memory uses a rotating selector to control the ratcheted manner of operation. Also, the memory is capable of simultaneously servicing each of a number of inputs and a number of outputs to which the memory is connected.