Patents Assigned to Sun Microsystems
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Patent number: 7209935Abstract: A garbage collector that employs the train algorithm to manage a generation in a computer system's dynamically allocated heap maintains for each of the generation's cars a respective remembered set that identifies all locations where references to objects in that car have been found by scanning locations identified by the mutator as having been modified. To avoid some of the expense of remembered-set updating, the collector refrains from attempting to add to a remembered set any reference located in a car that will be collected during the next collection increment. Additionally, if no mutator operation will occur before a collection set of one or more cars will be collected, any reference located outside that collection set but referring to an object within the collection set is not recorded in a remembered set but is recorded instead in a scratch-pad list of entries that identify references to collection-set objects that need to be evacuated.Type: GrantFiled: November 27, 2002Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventor: Alexander T. Garthwaite
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Patent number: 7210026Abstract: A processor includes a set of registers, each individually addressable using a corresponding register identification, and plural virtual registers, each individually addressable using a corresponding virtual register identification. The processor transfers values between the set of registers and the plural virtual registers under control of a transfer operation. The processor can include a virtual register cache configured to store multiple sets of virtual register values, such that each of the multiple sets of virtual register values corresponds to a different context. Each of the plural virtual registers can include a valid bit that is reset on a context switch and set when a value is loaded from the virtual register cache. The processor can include a virtual register translation look-aside buffer for tracking the location of each set of virtual register values associated with each context.Type: GrantFiled: June 28, 2002Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventor: Peter C. Damron
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Patent number: 7209996Abstract: In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plurality of cache bank memories in communication with the at cores through the crossbar is provided. Each of the plurality of cache bank memories are in communication with a main memory interface. In another embodiment a buffer switch core in communication with each of the plurality of cache bank memories is also included. A server and a method for optimizing the utilization of a multithreaded processor core are also provided.Type: GrantFiled: October 16, 2002Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventors: Leslie D. Kohn, Kunle A. Olukotun, Michael K. Wong
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Patent number: 7210066Abstract: A method for analyzing a test coverage of a software application specification by a test suite is provided. The method includes reading an assertion document for a specification. The assertion document has a corresponding tagged assertion for each assertion in the specification. Each tagged assertion is defined in a markup language. The method also includes reading a static file for defining tests of the test suite. The static file is defined in the markup language. The test suite is divided into tests and each test is divided into test cases. The static file is configured to include an entry for each test case and each entry is configured to include tagged assertions tested by the test case. Also included in the method is correlating each of the tagged assertions in the assertion document with the test cases in the static file so as to determine test coverage of the specification.Type: GrantFiled: December 31, 2002Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventors: Ramesh Babu Mandava, Jean-Francois Arcand
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Patent number: 7210006Abstract: A read-to-write-back transaction may allow I/O subsystems (or other devices) to perform a write to a portion of a cache block without gaining ownership of the cache block and requiring that it respond to foreign requests for the cache block. In response to an I/O subsystem initiating a read-to-write-back transaction, the device owning the cache block conveys the cache block to the I/O subsystem, and the I/O subsystem may perform partial or entire writes to the cache block. Subsequently, the cache block is written back to a memory subsystem from the I/O subsystem. The system is implemented such that these operations may be viewed logically as an atomic operation with respect to other coherence transactions to the same cache block, and thus the I/O subsystem need not become the owner of the cache line during performance of the read-to-write-back transaction.Type: GrantFiled: June 30, 2003Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventor: Robert E. Cypher
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Patent number: 7209960Abstract: A method and apparatus is provided for saving and loading Java applet data to and from, respectively, a local file system of a client computer system. It is not necessary to render the local file system accessible to the Java applet to save and load the Java applet data. Thus, the Java applet data is saved and loaded without compromising the security of the local file system and without requiring special certification of the Java applet.Type: GrantFiled: September 20, 2002Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventor: Pavel S. Veselov
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Patent number: 7209939Abstract: A computer system for multiplying a first matrix and a second matrix that reduces rounding error, including a processor, a memory, a storage device, and software instructions stored in the memory for enabling the computer system, under the control of the processor, to perform obtaining a first set of dimension values for the first matrix and a second set of dimension values for the second matrix, selecting one of a plurality of multiplication permutations if the first set of dimension values and the second set of dimension values are greater than a crossover value, multiplying the first matrix by the second matrix using the multiplication permutation and a Strassen-Winograd method, recursively sub-dividing the first matrix and the second matrix producing a set of sub-matrix products and a recursion tree, and propagating the set of sub-matrix products up the recursion tree to produce a product matrix.Type: GrantFiled: February 10, 2003Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventors: Rick R. Castrapel, John L. Gustafson
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Patent number: 7207040Abstract: An invention is provided for affording thread priority control in a distributed computer system. At least one task is executed on a server, where each task includes a task identifier and a priority value. In addition, a change priority message, which includes priority value and a task identifier, is received over a network. In response, the priority value of a specific task having the same task identifier as the task identifier of the change priority message is set equal to the priority value of the change priority message. As a result, the specific task is executed at a priority level relative to the priority value of the specific task.Type: GrantFiled: August 15, 2002Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Konstantin I. Boudnik, Weiqiang Zhang
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Patent number: 7205979Abstract: Apparatus is disclosed for generating control signals for the manipulation of virtual objects in a computer system according to the gestures and positions of an operator's hand or other body part. The apparatus includes a glove worn on the hand which includes sensors for detecting the gestures of the hand, as well as hand position sensing means coupled to the glove and to the computer system for detecting the position of the hand with respect to the system. The computer system includes circuitry connected to receive the gesture signals and the hand position signals for generating control signals in response thereto. Typically, the control signals are used to manipulate a graphical representation of the operator's hand which is displayed on a monitor coupled to the computer system, and the graphical representations of the operator's hand manipulates virtual objects or tools also displayed by the computer.Type: GrantFiled: July 17, 2002Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Thomas G. Zimmerman, Jaron Z. Lanier
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Patent number: 7206958Abstract: Given two synchronous clocks which transact data from a transmitter element to a receiver element which are analyzed by static timing, the interval between the transmitting data launch clock edge and the receiving capture clock edge is adjusted from the clock waveforms provided in order to represent the worst case slack situation between these two clocks over time. The amount of this adjustment is determined without unrolling (enumerating) all possible launch/capture pairs for these clocks. The greatest common divisor (GCD) of a transmit clock frequency and a receive clock frequency is determined. An effective phase shift is determined by performing a MOD operation between the GCD and an offset of the transmitter and receiver clocks. An algorithm uses the GCD and effective phase shift to determine a launch/capture interval that corresponds to a critical slack condition.Type: GrantFiled: October 21, 2003Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Jeannette N. Sutherland, Robert E. Mains, Matthew J. Amatangelo
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Patent number: 7206976Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide for managing exposure to failure for computer-based systems. Information about a computer-based system is asynchronously received. An exposure level to failure of the computer-based system is calculated based on the received information. A stability of the computer-based system is determined based on the exposure level. A stability indication is output responsive to the determined stability.Type: GrantFiled: October 22, 2003Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Michael J. Wookey, Paris E. Bingham, Jr., Matthew J. Helgren
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Patent number: 7206836Abstract: Data stored within a cluster may be distributed among nodes each storing a portion of the data. The data may be replicated wherein different nodes store copies of the same portion of the data. In response to detecting the failure of a node, the cluster may initiate a timeout period. If the node remains failed throughout the timeout period, the cluster may copy the portion of the data stored on the failed node onto one or more other nodes of the cluster. If the node returns to the cluster during the timeout period, the cluster may maintain the copy of the data on the previously failed node without copying the portion of the data stored on the failed node onto any other nodes. By delaying self-healing of the cluster for the timeout period, an unbalanced data distribution may be avoided in cases where a failed node quickly rejoins the cluster.Type: GrantFiled: September 23, 2002Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Darpan Dinker, Pramod Gopinath, Mahesh Kannan
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Patent number: 7207037Abstract: A method for arithmetic expression optimization includes receiving an operator and at least one operand of a first instruction defined for a first processor having a first base. The method also includes converting the first instruction to a second instruction optimized for a second processor having a second base smaller than the first base when the at least one operand does not carry potential overflow beyond the second base or when the operator is insensitive to overflow. The method also includes converting instructions in an instruction chain to a wider base larger than the second base and smaller or equal to the first base when the at least one operand carries potential overflow beyond the second base and when the operator is sensitive to overflow. The chain is bounded by the second instruction and a third instruction that has been previously optimized and is the source of the potential overflow.Type: GrantFiled: November 12, 2003Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventor: Judith Schwabe
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Patent number: 7206963Abstract: A system and method for providing switch redundancy in a computer network comprises two or more separate servers that are connected together to allow the servers to operate as one complete system that may continue to operate even in the event that one server becomes unable to provide switching functions. In one exemplary embodiment, the computer network includes two or more servers and a server bridging assembly. Two or more servers are interconnected via the server bridging assembly such that, in the event that a switch located in one of the servers fails, the switch located in the other server can be used to provide switching functions for both servers. As a result, the servers are interconnected to provide redundancy.Type: GrantFiled: June 12, 2003Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Balkar S. Sidhu, Ramani Krishnamurthy, Kaamel Kermaani
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Patent number: 7206934Abstract: Embodiments of a distributed index mechanism for indexing and searching for identity information in peer-to-peer networks. In one embodiment, a distributed index may be used to store identity information in a decentralized manner on a plurality of peer nodes. The identity information may be used, for example, to authenticate users. Distributed indexes may allow identity information to be spread across multiple peer nodes so that the load is spread among the various peer nodes. In one embodiment, the distributed index may be a distributed hash table. One embodiment of a distributed index of identity information may be implemented in peer-to-peer networks implemented according to a peer-to-peer platform including one or more peer-to-peer platform protocols for enabling peer nodes to discover each other, communicate with each other, and cooperate with each other to form peer groups and share network resources.Type: GrantFiled: September 26, 2002Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Kuldipsingh A. Pabla, Akhil K. Arora
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Patent number: 7205810Abstract: A phase shift driver for phase shifting an input clock signal at a first phase to generate an output signal at a second phase without missing subsequent input signals. Input logic circuitry of the phase shift driver may receive an input signal at a first phase. Output logic circuitry of the phase shift driver may generate an output signal at a second phase relative to the input signal. The output signal may be a phase-shifted version of the input signal. A reset control circuit may receive a feedback signal from the output logic circuitry and an intermediate signal from the input logic circuitry and generate a reset signal based on the received feedback and intermediate signals. The reset control circuit may control a pulse width of the reset signal to reset the input logic circuitry within a period of time before the input logic circuitry receives a subsequent input signal.Type: GrantFiled: September 29, 2005Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Jungyong Lee, Heechoul Park
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Patent number: 7206906Abstract: Provided is a method and apparatus for registering requests to access physical memory in a physical address mapping framework. Specifically, a device can register in the physical address mapping framework before accessing physical memory, thus permitting an operating system to identify the device when it is necessary to relocate pages in physical memory. The physical address mapping framework can be any structure that permits registration. For example, the structure can be a list or a tree. When relocating physical memory, all accesses registered in the physical address mapping framework are restricted. Then, the device is notified to stop accessing physical memory via information stored in the physical address mapping framework. After the relocation, the device is notified to resume accessing physical memory via information stored in the physical address mapping framework.Type: GrantFiled: March 10, 2004Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Udayakumar Cholleti, Michael T. Clayton, Anthony G. Sumpter
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Patent number: 7206827Abstract: A dynamic administration framework for server systems. A generation mechanism may generate one or more components of the administration framework from meta-information describing persistently stored configuration information. Components providing an in-memory representation of configuration information and components representing business logic of the server may be generated. A user interface may be generated which may be used to administer the generated components. A configuration API may be provided that provides a transparent interface to the persistent store, abstracting storage format and location from clients of the configuration API. A generated administration framework may be compiled with application server or system-specific components. The compiled system may then be used at runtime. One embodiment may include an event notification mechanism that may allow changes in configuration data to be propagated to one or more servers.Type: GrantFiled: July 25, 2002Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Sridatta Viswanath, Jeetendra Kaul, Akm N. Islam, Michael C. Hulton, Ludovic J. Champenois
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Patent number: 7206916Abstract: A method of performing a fast information compare within a processor which includes performing a more significant bit compare when information is loaded into a translation lookaside buffer, storing a result of the more significant bit compare within the translation lookaside buffer as part of an entry containing the information, and using the result of the more significant bit compare in conjunction with results from a compare of less significant bits of the information and less significant bits of compare information to determine whether a match is present. The more significant bit compare compares more significant bits of the information being loaded into the translation lookaside buffer with more significant bits of compare information.Type: GrantFiled: March 8, 2004Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Michael D. Estlick, Harry R. Fair, III, David R. Akeson
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Patent number: D541268Type: GrantFiled: September 8, 2005Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventors: Christopher H. Frank, Dimitry Struve, Jeffrey T. Paladini