Abstract: A method and apparatus for handling window management instructions without post serialization in an out-of-order multi-issue processor includes an instruction decode unit arranged to decode the window management instruction. A plurality of register windows are indexed by a current window pointer, and a working copy of the current window pointer is stored in a register in the instruction decode unit. The instruction decode unit uses the working copy of the current window pointer to handle the window management instruction.

Abstract: A computer system may include several integrated circuits and a routing circuit configured to route several data streams between the integrated circuits. The routing circuit includes several input ports, several output ports, and a signature analysis register coupled to one of the output ports. The signature analysis register is configured to collect data conveyed via the output port dependent upon whether the signature analysis register receives a tag identifying one of the plurality of data streams.

Abstract: A method and apparatus are provided for controlling the power consumption of a semiconductor device such as a CPU or other form of processor that is operable to process a sequence of instructions. The device includes a monitor for checking the power consumption of the device, in order to detect any significant change in power consumption (which can cause problems for the power supply circuitry). In order to mitigate such change, one or more dummy instructions are inserted into the sequence of instructions. The dummy instructions do not affect the logical processing, but are selected in order to limit the change in power consumption. Thus if the change in power consumption represents an increase, then dummy instructions are selected that do not require much current. Conversely, if the change in power consumption represents a decrease, then dummy instructions are selected that draw a relatively large amount of current.

Abstract: A system for selecting routing information from a routing table describing alternative routes between end nodes. The routing table represents a set of minimum cost, deadlock-free routes between end nodes. The selected routing information is included in forwarding tables, and sent to networking devices in the network. The selected routing information is optimized for at least one network performance metric, such as overall network capacity or fault tolerance. Capacity optimization is obtained by selecting from alternative routes stored within the routing table such that the standard deviation of the number of routes flowing over each link in the network is minimized. Fault tolerance optimization is achieved by selecting from the alternative routes stored in the routing table such that the selected route for a given end node pair has a “failover” route with a maximum number of dissimilar links from the selected route.

Abstract: A test apparatus including a data interface configured to couple with at least one of a test device and a baseline device, and a computing device configured to perform a method including performing a first benchmark on a baseline device for a predetermined time interval, resulting in a first dataset representing work performed by the baseline devices, performing a second benchmark on a test device for the predetermined time interval resulting in a second dataset representing work performed by the test device, and using a heuristic including a number of tests to determine whether the test device has an acceptable level of performance relative to the baseline device.

Abstract: A microchip configured to reliably transmit data is provided. The microchip includes a memory region and a selection module configured to select a portion of the data from the memory region. An error checking module configured to calculate a value derived from the selected portion of the data is provided. A pointer region including a plurality of object pointers is included. One of the object pointers is associated with an address of the portion of the data. The object pointer associated with the address is configured to receive a signal indicating an error associated with the transmission of the data. A scheduler module in communication with each of the plurality of object pointers is provided. The scheduler module is configured to schedule re-transmission of the selected portion of the data. A system and a method for reliably transmitting data between microchips are also provided.

Abstract: One embodiment of the present invention provides a system that applies personalized rules for handling e-mail messages to e-mail messages within an e-mail server. During operation, the system connects to the e-mail server from a remote computer system on behalf of a user. Next, the system applies the personalized rules to e-mail messages received for the user at the e-mail server. This involves applying actions specified in the personalized rules to the e-mail messages. Next, the system disconnects from the e-mail server so that the connection does not have to be maintained.

Abstract: Converting a document in a small device format and merging the converted document with an original version of the document in an office productivity format. A document on a server may be converted to a small device format. Some information may be dropped from the document during conversion. The converted document may be transferred to a small device for editing. The edited document may be transferred back to the server for synchronization with the original document. After transferal, the edited document may be converted back to the original document format on the server and analyzed to determine differences between the edited document and the original document. The determined differences may be applied to the original document to merge the small device document with the original document. Information that was lost during the original conversion of the document may be restored to the merged document during the conversion/merge process.

Abstract: One embodiment of the present invention provides a system that facilitates capacitive inter-chip communication. During operation, the system first determines an alignment between a first semiconductor die and a second semiconductor die. Next, electrical signals are selectively routed to at least one interconnect pad in a plurality of interconnect pads based on the alignment thereby facilitating communication between the first semiconductor die and the second semiconductor die. The plurality of interconnect pads can include transmitting pads, receiving pads, and transmitting and receiving pads. The alignment may be determined continuously or at times separated by an interval, where the interval is fixed or variable. Several variations on this embodiment are provided.

Abstract: A data representation language representation of the state of a process executing on a client or service in a distributed computing environment may be created. The representation may include a computation state of the device and/or virtual machine on which the process is executing, wherein the computation state of the device and/or virtual machine comprises information about the execution state of the process on the device and/or virtual machine. A process state may include, but is not limited to: threads, all objects referenced by the threads, transient variables created during the execution of the process, objects and their data, etc. In one embodiment, data describing one or more leases representing grants of access to external services, obtained from spaces by the process, may also be stored with the process state. The data representation language representation of the state of a process may be moved from node to node within the distributed computing environment.

Abstract: A graphical computing system comprising a control unit and a set of edge processing units. The control unit (a) receives a surface primitive, (b) transfers edge specifying information for each edge of the surface primitive to a corresponding one of the edge processing units, and (c) transfers a horizontal address CX and a vertical address CY of a current pixel to the edge processing units. Each of the edge processing units computes trimming information for the current pixel with respect to the corresponding edge using the horizontal address CX and vertical address CY. The trimming information specifies a portion of the corresponding edge which intersects the current pixel. The control unit collects the trimming information from the edge processing units and transmits an output packet including the addresses CX and CY of the current pixel along with the collected trimming information.

Abstract: A method and system are provided for generating a data structure representative of a fault tree for a system. One embodiment of the method includes providing one or more input files comprising a source code description of the fault tree. The source code description has a plurality of statements specifying events and propagations in the fault tree, where a propagation represents a cause and effect linkage between events. The method further includes compiling the input files in source code into the data structure.

Abstract: A fabric driver on a host system connected to a fabric may include an API for an administration application to query and obtain a list of devices connected to a fabric host adapter port(s). The fabric driver may execute this query and obtain the list of devices by querying a fabric name server. One or more direct attach devices may also be discovered. For direct attach devices, like private loop topologies, operating system device nodes may be created during driver attach. However, for fabric topologies the fabric driver provides a list of devices visible through the fabric host adapter port by querying the fabric name server and supplies this list to the administration application in response to the administration application's request. A user may then select devices from this list to be onlined. A dynamic persistent repository may be maintained of devices onlined using this on-demand node creation process.

Abstract: A dual match line circuit may include precharge logic configured to precharge each of a hit match line, a miss match line and an evaluate node to an asserted state, where a coupling device couples the hit and miss match lines to the evaluate node. The miss match line may discharge through a number of load devices that may be activated by respective miss signals. The hit match line may be additionally coupled to discharge through a pair of devices connected in series, one of which may be activated by a hit signal, and the other of which may be activated by the miss match line. The hit and miss match lines may be electrically isolated from one another, such that when any of the respective miss signals is asserted, current from the hit match line does not discharge through the miss match line.

Abstract: When a thread of program execution on a computer system is executing a critical code section, i.e., a code section whose preemption could result in inconsistency, it asserts an indicator of that fact. When the system's scheduler reschedules the thread for execution, it determines whether the indicator is asserted. If the indicator is asserted, the scheduler does not cause the thread immediately to resume execution where the thread left off when it was preempted. Instead, the scheduler has the thread's signal handler execute in such a manner that the thread performs inconsistency-avoiding operations.

Abstract: A hardware trace unit is integrated into a computer system that has a main memory. The trace unit includes registers that contain information defining a location in main memory, and has an input connection. This is used to eavesdrop on communications in the computer system, thereby obtaining information about the state and/or operation of the system. A trigger mechanism then compares the information received against one or more trigger conditions, such as whether a particular event has occurred. Responsive to the trigger conditions being satisfied, the trace unit generates an output record containing diagnostic information. This is sent for storage in the main memory of the computer at the location defined in the registers.

Abstract: A resource-constrained device such as a smart card or the like includes memory for storing an application software program comprising an object-oriented, verifiable, platform-independent, type-safe and pointer-safe sequence of instructions. The device can also include a virtual machine implemented on a microprocessor where the virtual machine is capable of executing the sequence of instructions. Each instruction includes an operation code, and each data manipulation instruction is specific to a particular data type. The application program can be stored on a computer-readable medium prior to being received by the resource-constrained device. Methods of using such an application program, including accessing the program over the Internet and downloading it to a smart card, also are disclosed.

Abstract: A system that facilitates reducing uncertainty in a quantized signal. During operation, the system measures a quantized output signal from a sensor. Next, the system obtains an initial value for an uncertainty interval for the quantized output signal. The system then margins the quantized output signal high by introducing a controlled increase in the mean of the quantized output signal to produce a high-margined quantized output signal. Next, the system measures the high-margined quantized output signal from the sensor. The system then uses information obtained from the high-margined quantized output signal to reduce the uncertainty interval for the quantized output signal.

Abstract: A method for evaluating portable electronic devices includes performing a first benchmark on a baseline device for a predetermined time interval, resulting in a first dataset representing work performed by the baseline device. The method further includes performing a second benchmark on a test device for the predetermined time interval resulting in a second dataset representing work performed by the test device. Finally, the test device is determined to be initially acceptable if the total amount of work performed by the test device and the total amount of work performed by the baseline device differ by less than an acceptance threshold, and is determined to be finally acceptable by performing a quotient test on the data.

Abstract: A method for determining a maximum IR drop on a power grid of a circuit is disclosed. The method includes dividing a reference timing signal into multiple bins. Each one of the bins having a corresponding bin duration. The bins being divided by a corresponding fuzzy boundaries. Each one of the fuzzy boundaries having a corresponding boundary duration. Each one of the of bins is analyzed including selecting one of the bins, identifying a first set devices that transition to their corresponding maximum current states during the selected bin and identifying a second set of devices that transition to their corresponding maximum current states during at least one of the boundaries of the selected bin, but not within the selected bin. A maximum current demand equal to a sum of the maximum current states of the first and second plurality of devices is calculated. A system for testing a circuit is also disclosed.