Abstract: In one embodiment, a node comprises at least one memory control unit configured to couple to an industry standard memory interface for coupling to a memory; and at least one coherence unit configured to transmit and receive coherence messages to and from other nodes to maintain coherent memory among the nodes. The coherence messages are conveyed on a second interface to which the coherence unit is coupled, wherein the second interface includes at least a physical layer as specified by the industry standard memory interface.

Abstract: We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms.

Abstract: In one embodiment, a node comprises a plurality of processor cores, coherency control circuitry coupled to the plurality of processor cores, and at least one coherence unit coupled to the coherency control circuitry. Each processor core is configured to have a plurality of threads active and each processor core includes at least one first level cache. The coherency control circuitry is configured to manage intranode coherency among the plurality of processor cores. The coherency unit is configured to couple to an external interface of the node, and is configured to transmit and receive coherence messages on the external interface to maintain coherency with at least one other node having one or processor cores and a coherence unit. In another embodiment, a system comprises an interconnect and a plurality of nodes coupled to the interconnect.

Abstract: One embodiment of the present invention provides a system with a mechanism that facilitates determining whether a kernel stack will overflow during development of an operating system. During execution of the operating system, the operating system executes a procedure. Upon entering the procedure, after the current stack pointer has been automatically adjusted to provide stack space for the procedure, the system retrieves the current stack pointer for the process, and determines the stack limit for the process. The system then compares the current stack pointer to the stack limit to determine if the process will cause, or is likely to cause a stack overflow. If a stack overflow will occur, or is likely to occur, the system indicates the existence of a stack overflow condition.

Abstract: A computer system may include a client subsystem, another client subsystem, and a network coupled to the client subsystems. The network includes several network slices. One of the client subsystems is configured to convey a packet to the other client subsystem by conveying each of several slices of the packet on a respective one of the network slices. The client subsystem also conveys redundant information associated with the packet on at least one additional network slice. The redundant data is usable to regenerate at least one of the slices of the packet.

Abstract: A method and apparatus for generating a noise circuit model for an electronic circuit includes analyzing the electronic circuit to determine a first circuit parameter for a victim and aggressor circuits and a second circuit parameter for the aggressor circuits, ordering the aggressor circuits based on their first and second circuit parameters, setting a current model parameter of the circuit model to an initial value, selecting a first aggressor circuit, determining whether to reduce the selected aggressor circuit into a virtual attacker model based on its first circuit parameter, updating the current model parameter in accordance with either the selected aggressor circuit or its virtual attacker model to be inserted, inserting either the selected aggressor circuit or its virtual attacker model to the circuit model, for each aggressor circuit.

Abstract: One embodiment of the present invention provides a system that detects a failure sequence that leads to undesirable computer system behavior and that subsequently takes a corresponding remedial action. During operation, the system receives instrumentation signals from the computer system while the computer system is operating. The system then uses these instrumentation signals to determine if the computer system is in a failure sequence that is likely to lead to undesirable system behavior, such as a system crash, wherein the determination involves considering predetermined multivariate correlations between multiple instrumentation signals and a failure sequence that is likely to lead to undesirable system behavior. Next, if the computer system is in a failure sequence that is likely to lead to undesirable system behavior, the system takes a remedial action.

Abstract: A computing system comprises multiple domains, each having an independent boot process. This boot process involves the selection of one boot option from a list of potentially multiple boot options available to the domain. The apparatus further comprises a centralized configuration utility, and a boot controller within each domain. The boot controller supplies said configuration utility with the list of boot options available to that domain. The configuration utility allows a user to specify en bloc the boot option for multiple domains. This information is then passed back to the boot controllers of the respective domains, which then boot in accordance with the boot option specified by said configuration utility.

Abstract: A method for statically allocating a procedure return address includes separating a software program including multiple procedures into a cyclic part and an acyclic part, allocating a static address for the return address of a procedure in the acyclic part and modifying at least one of the procedures to refer to the static address for the procedure return address.

Abstract: The system for managing bandwidth in a remote services system provides an infrastructure that enables a customer to control bandwidth utilization in accordance with specified network performance criteria. The architecture is broadly comprised of a bandwidth management system that operates in conjunction with aggregation Mid-level Manager and application Mid-level Managers controlled by the service provider. The customer deployment can be implemented using a single proxy or a plurality of proxies. Customer access to system resources is controlled by a service provider web-access portal controlled by the service provider.

Abstract: Improved techniques for representation of Java data types in virtual machines are disclosed. The techniques can be implemented to represent signatures of Java methods as arrays of references. Each of the references in an array can represent a parameter for a Java method. Accordingly, a signature can be represented as an array of references, wherein each reference in the array can reference a Java type indicator or an internal class representation. The Java type indicator represents a Java primitive type (e.g., byte, integer, double, etc.) The internal class representation is typically the representation of a Java class as represented in a virtual machine. As will be appreciated, an array organization allows for more efficient access to information. Thus, unlike conventional techniques, there is no need to start at the beginning of the signature and sequentially read it to find a particular parameter's data type.

Abstract: One embodiment of the present invention provides a system for type tagging values in a compiled activation frame in a lazy manner to facilitate garbage collection. This system operates in a mixed-mode environment that supports both interpretation of byte codes and execution of compiled native code. Upon receiving an invocation of a method, the system creates an activation frame for the method on the execution stack. If the method is executing in interpreted mode, the interpreter maintains a tag for each value in the activation frame during execution. The tag indicates whether the value is a reference type or a primitive type. However, if the method is executing in compiled mode, the system allocates space for tags for each value in the activation frame, but does not fill in the tags during execution. This allows the tags to be filled in at a future time when needed.

Abstract: A graphics system comprising a set of rendering processors and a series of filtering units. Each of the rendering processors couples to a corresponding one of the filtering units. Each rendering processor RP(K) is configured to (a) generate a stream of samples in response to received graphics primitives, (b) add a dither value DK to a data component of each the samples in the stream to obtain dithered data components, (c) buffer the dithered data components in an internal frame buffer, and (d) forward a truncated version of the dithered data components to the corresponding filtering unit. The filtering units are configured to perform a weighted averaging computation on the truncated dithered data components in a pipelined fashion to determine pixel data components.

Abstract: A method and system for web based graphical control components. Specifically, the present invention describes a method of graphically displaying a graphical user interface (GUI) control component within a hypertext markup language (HTML) web page. The present invention optionally displays a label associated with a displayed GUI control component. A JavaScript routine is invoked in response to user input, and based thereon a selected image file is selected from a plurality of image files. The plurality of image files correspond to respective user selectable options for responding to the label. The selected image file is then displayed in the GUI control component on the HTML web page. The JavaScript routine employs a unique naming scheme for name tags of a plurality of sequentially associated slave objects of a master object for more concise referencing.

Abstract: An interlock system may control a sequence of installation of circuit board assemblies into a chassis and/or removal of the circuit board assemblies from the chassis. In one embodiment, an interlock member may inhibit installation of one circuit board assembly until another circuit board assembly has been fully installed in a chassis. An interlock member may also inhibit removal of the one circuit board assembly until another circuit board assembly has been removed. In some embodiments, an interlock member may inhibit use of injector/ejectors to inject or eject a circuit board.

Abstract: A computer security system utilizing smart cards for computer access. A system for home or small business use generally is presented in which smart cards are utilized to gain access to computer functions. The user is presented with a login prompt that permits login using the smart card. The user is permitted to bypass use of the smart card and obtain access to the computer system, but such use of the computer system is logged for review by an administrator.

Abstract: Network identities for components (e.g., server blades) of a multi-domain computer system (e.g., a server blade system) are stored in a connection framework (e.g., a carrier for the server blades) and copies thereof are stored in two or more support units (e.g., service processors for the carrier). These multiple copies can then be used to ensure the integrity of network identities that are allocated to the system units by the support units.

Abstract: A method and mechanism for managing timers in a multithreaded processing system. A storage device stores a plurality of count values corresponding to a plurality of timers. A read address generator is coupled to convey a read address to the storage device. The read address generator is configured to maintain and increment a first counter. In response to determining the counter does not equal a predetermined value, the mechanism conveys a first read address for use in accessing a count value in the storage device. In response to determining the count equals the predetermined value, the mechanism conveys a second read address for use in accessing a count value in the storage device. The predetermined value is utilized to repeat accesses to a given count value a predetermined number of times.

Abstract: An apparatus and method for interfacing with a metrics database is provided for getting metrics data and grouping metrics data in response to a query. The metrics database interface gets metrics data by retrieving a set of metrics data from the metrics database in response to a query and determining a set of unique tags. The metrics database interface also groups a set of metrics data in response to a query so that the group can be referenced in a subsequent query.

Abstract: A method and apparatus for utilizing a non-secure file server for storing and sharing data securely only among clients and groups authorized to read and modify the data. A first client that desires to store data on the file server encrypts the data with a first encryption key having an associated first decryption key. The client encrypts the first decryption key with a second encryption key having an associated second decryption key known to the first client. Additionally, the first decryption key is encrypted with respective encryption keys of other clients or groups intended to have access to the data stored on the file server and the clients and groups retain their respective decryption keys. All of the encrypted first decryption keys are stored within an access control list in association with the encrypted data on the non-secure file server.