Abstract: In one embodiment, a processor comprising at least one translation lookaside buffer (TLB) and a control unit coupled to the TLB. The control unit is configured to track whether or not at least one update to the TLB is pending for at least one of a plurality of strands. Each strand comprises hardware to support a different thread of a plurality of concurrently activateable threads in the processor. The strands share the TLB, and the control unit is configured to delay a demap operation issued from one of the estrands responsive to the pending update, if any.

Abstract: A heat sink uses a ferrofluid-based pump assembly for controlling the direction of nanofluid flow within the heat sink. The nanofluid is thermally conductive and absorbs heat from a heat source, which is then directed away from the heat source by the ferrofluid-based pump assembly. The ferrofluid-based pump assembly uses a motor to rotate at least one magnet so as to rotate ferrofluid contained in the ferrofluid-based pump assembly. The direction of nanofluid flow within the heat sink is dependent on the movement of ferrofluid in the ferrofluid-based pump assembly.

Abstract: The present invention provides methods and memory structures for efficient tracking and recycling of physical register assignments. The disclosed methods and memory structures each provide an approach to reduce the size of the memory structures needed to track the usage of the physical registers and the recycling of these registers.

Abstract: A plurality of processors on a chip is operated in lockstep. A crossbar switch on the chip couples and decouples the plurality of processors to a plurality of banks in a level-two (L2) cache. As data is stored in a first bank of the L2 cache, the old data at that location is passed through the crossbar switch to a second bank of the L2 cache that is functioning as a first-in-first-out memory (FIFO). Thus, new data is cached at a location in the first bank of the level-two cache, i.e., stored, and old data, from that location, is logged in the second bank of the level-two cache. The logged data in the second bank is used to restore the first bank to a known prior state when necessary.

Abstract: An invention is provided for affording asynchronous fault-tolerant and adaptive communication in a distributed computing environment. The invention includes periodically updating a stored connection state value, which is received from an application. The connection state value indicates the number of data elements processed by the application. An interruption in a digital connection is then detected on a network between two endpoints. Upon detection, the stored connection state value is exchanged with the opposite endpoint over the network. In this manner, remaining data elements of the transaction can be received sequentially over the network from the opposite endpoint. In particular, the remaining data elements begin with a data element at a point indicated by the connection state value plus one.

Abstract: A service gateway connects at least one local client to an external network. The service gateway is operable to hold at least one service module for providing a corresponding service and to maintain a record identifying each service module held by the service gateway with an associated pointer to that service module. The service gateway includes a control mechanism providing a number of functions. The control mechanism is operable in response to a request for a service provided by a service module not present at the service gateway, to send a message to an external source for resolving the absence of a service module at the gateway in one or more iterations until a response from the external service identifies information including a service module held by the gateway that enables resolution of the absent service module(s).

Abstract: A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is provided. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit includes a first counter arranged to increment for each of the plurality of single precision floating point instructions forwarded down a pipeline; a second counter arranged to increment for each of the plurality of double precision floating point instructions forwarded down the pipeline; a first mask register and a second mask register. The first mask register is updated by each of the single precision floating point instructions forwarded and the second mask register is updated by each of the double precision floating point instructions forwarded.

Abstract: A method and apparatus folds a circuit having a plurality of transistors. The folding includes: (a) determining a number of folds to realize a desired layout of the circuit based on a netlist of the circuit, a folded circuit having a number of fingers corresponding to the number of folds; (b) creating a single-finger layout for the circuit, the single-finger layout including a respective smaller transistor for each of the original transistors, each of the smaller transistors having a size which is an original size of the corresponding original transistor divided by the number of the fingers, the smaller transistors in the single-finger layout having an arrangement the same as an original arrangement of the original transistors in the circuit; and (c) tiling the single-finger layout for the number of folds such that each single-finger layout abuts an adjacent single-finger layout.

Abstract: A method for determining a physical location of a source is provided. The method includes receiving an acoustic signal from a source placed within an acoustic monitoring area. The method also includes processing a received acoustic signal. The processing is configured to use data from at least two sensors. Also included is identifying an approximate localized point in the acoustic monitoring area. The approximate localized point defines a physical location of the source. The method further includes reporting the physical location of the source over a network.

Abstract: A method for detecting an invalid pointer including a source component and a target component, involving selecting a virtual source memory address for the source component wherein the virtual source memory address is within a first valid virtual address range, selecting a virtual target memory address for the target component wherein the virtual target memory address is within a second valid virtual address range, numerically combining the virtual source memory address and the virtual target memory address to obtain a new virtual source memory address, and writing the virtual target memory address into a memory location referenced by the new virtual source memory address, wherein writing the virtual target memory address triggers an action by a memory management unit (MMU) if the new virtual source memory address is an invalid memory location.

Abstract: One embodiment of the present invention provides a system that migrates a layout of a cell which is used in integrated circuit design. During operation, the system receives a layout for the cell, wherein one or more layers of the cell contain tracks for metal wires. The system then determines how many tracks are to be inserted into the cell. Next, the system inserts one or more extra tracks between the tracks in the cell. The system subsequently adjusts the widths of the inserted tracks and the original tracks to increase the total number of tracks within the cell while maintaining the metal wires at the center of their original tracks.

Abstract: One embodiment of the present invention provides a monitoring system that detects anomalies in data gathered from sensors in a computer system. During operation, the monitoring system samples data from a plurality of sensors located at various sampling points throughout the computer system. Next, the monitoring system interpolates the data from the sampling points to produce a real-time digitized surface. The monitoring system then subtracts a reference digitized surface from the real-time digitized surface to produce a residual digitized surface. Finally, the monitoring system applies a multi-dimensional sequential probability ratio test (SPRT) to the residual digitized surface to detect anomalies in the residual digitized surface which indicate an impending failure of the computer system.

Abstract: A smart card contains potentially multiple applications, each containing an application identifier (AID). Each application also incorporates an AID interpreter for providing access to the AID. This is achieved by making a request to the AID interpreter to provide the AID for the application. In response, the AID interpreter retrieves a first component of the AID. This first component is logically internal to the AID interpreter. The AID interpreter also retrieves a second component of the AID. This second component is logically external to the AID interpreter and is indicative of a state relevant to the application, such as a current balance in the card. The first and second components of the AID are then combined in order to generate the AID for providing in response to the request.

Abstract: A system and method for automatically identifying a desirable reconfiguration of computer system resources, using a perceptron to determine whether one resource configuration will likely be more efficient or more effective than a second configuration. An iterative solver identifies possible configurations or reconfigurations of the resources. A possible configuration is applied to the perceptron, which determines whether the new configuration is more attractive than an existing or baseline configuration, in terms of a predetermined objective function (e.g., cost, performance, resource utilization, throughput). If the new configuration improves the objective function, the new configuration may be automatically or manually applied through a dynamic reconfiguration operation.

Abstract: A cable management system for a component mounted in a rack includes a cable management arm and a bracket. The cable management arm may include a rear link attached to the rack and a forward link coupled to the rear link. The bracket may be attached to the component. A hanger pin may provided on the forward link. The hanger pin may couple with the bracket in a slot in the bracket. The hanger pin may apply a force to the bracket such that the hanger pin carries a portion of the weight of the forward link. In some embodiments, the cable management arm includes a pivot pin. The pivot pin may couple with a second aperture in the bracket. The hanger pin may ride along a slot as the forward link is rotated about the pivot pin with respect to the bracket.

Abstract: A method and apparatus for adjusting a frequency characteristic of a signal is provided. A transmitter circuit uses a driver circuit and a filter to generate the signal. The frequency characteristic of the signal is adjusted, or “equalized,” using a replica driver that adjusts the driver circuit and a voltage control circuit that adjusts the filter.

Abstract: A method for analyzing impact on binaries, software, and hardware of a planned software upgrade for a computer system. The method includes performing a configuration inventory for the computer system with profiles for the computer system of hardware, software including operating system software, middleware, applications, development tools, and third party software, application interfaces, and binaries. A set of upgrade rules, e.g., rules defining hardware and software requirements including interfaces, libraries, dependencies, and more, are accessed and the binary profiles are analyzed based on the upgrade rules to determine safe binaries and at-risk binaries. The at-risk binaries are further divided into subcategories based on risks of incompatibility with the planned software upgrade. The subcategories include failure, high risk, and low risk.

Abstract: An invention is disclosed for providing methods for parsing test results having diverse formats. Test results from executed test suites are identified. Test result formats of the test results are categorized. An order of the test results is tracked. A chain of parsers is assembled from individual parsers such that each individual parser is charged with parsing a particular test result format. Test results are parsed such that the data features that define attributes of the test results are identified where the attributes define pass, fail, and comments associated with the pass or fail.

Abstract: A floating point comparator circuit for comparing a plurality of floating point operands includes a plurality of analysis circuits, one for each of the floating point operands, configured to determine a format of each of the floating point operands based upon floating point status information encoded within each of the floating point operands, and a result generator circuit coupled to the analysis circuits, the result generator circuit configured to generate a result signal based on the format determined by each analysis circuit and based on a comparative relationship among the floating point operands. The format of each of the floating point operands may be from a group including: not-a-number (NaN), infinity, normalized, denormalized, zero, invalid operation, overflow, underflow, division by zero, exact, and inexact.

Abstract: Systems and methods for implementing an execution stack which stores frames for functions written in multiple programming languages are provided. The frames for functions written in different programming languages may be interleaved on the same execution stack. A data block on the execution stack may be utilized to traverse the execution stack around a frame by storing a stack pointer and frame pointer to a previous frame. Additionally, exceptions may be propagated, with conversion if necessary, through frames on the execution stack that are written in different programming languages.