Abstract: A method for lexically analyzing an input stream including invoking a multipurpose lexical analyzer, wherein invoking the multipurpose lexical analyzer comprises examining a parameter setting, scanning the input stream to obtain a token using a token definition, and determining whether to ignore the token using the parameter setting, returning the token to a calling process if the token is to be processed.

Abstract: Improved techniques for determining Java hashcode values for Java objects are disclosed. The techniques can be implemented to use a new Java Bytecode instruction which is suitable for execution by a Java virtual machine. As such, the new Java Bytecode instruction can be executed to determine Java hashcode value. Moreover, as will be appreciated, the Java hashcode values can be determined without invoking the Java method which is conventionally used to determine hashcode values. This means that the costly overhead associated with repeatedly invoking Java methods is avoided. In other words, operations that are conventionally performed each time this method is invoked need not be performed. As a result, the performance of virtual machines, especially those operating with limited resources (e.g., embedded systems), can be improved.

Abstract: A method for reading data from a memory module over a bi-directional bus is provided. The method initiates with issuing a read command. Then, a strobe signal is transitioned from a mid-rail state. In one embodiment, the strobe signal is transitioned to a logical low state. A read enable signal is then transitioned prior to a first falling edge of the strobe signal. The strobe signal represents an earliest availability for valid read data being available. The valid read data is read in response to the read enable signal transition. A microprocessor and a system wherein data is read over a bi-directional bus are included.

Abstract: A system that generates a dynamic trace of power consumption in a computer system. The system periodically polls current sensors and associated voltage sensors within the computer system to generate dynamic traces of currents and associated voltages for individual components within the computer system. The system then generates a dynamic trace of total power consumption for the computer system based on the dynamic traces of the currents and the associated voltages for the constituent components.

Abstract: A computer arrangement with a processor (5) and at least one memory unit (7, 9, 11, 13) connected to the processor (5) and including dynamic random access memory (13), wherein the computer arrangement is arranged to use but not to refresh at least part of the dynamic random access memory (13) while running a program.

Abstract: A method of computing overhead associated with executing instructions on an out-of-order processor which includes determining when a first instruction retires, determining when a second instruction retires, and calculating an overhead based upon subtracting when the first instruction retired from when the second instruction retired.

Abstract: Embodiments of a decentralized mechanism for detecting the presence of entities in a peer-to-peer network. In one embodiment, using pipes, a peer may uniquely and independently generate an identity for a peer-to-peer network entity. The identity may be used to probe the peer-to-peer network for presence of instances of the corresponding entity on other peers regardless of which peer the identity was generated on and without using a central identity repository or presence system. In one embodiment, net crawling may be used to map identities and resolve the locations of instances of the corresponding entities. An entity may move anywhere on the network, and the decentralized mechanism for detecting entity presence may be used to locate the instance(s) of the entity.

Abstract: Type safe linkage is ensured by establishing a constraint if a class references an attribute that is contained in another class. This constraint acts as a “promise” to later ensure type safe linkage. At some point later—such as at the earliest time that the type is loaded by both loaders—the constraint is verified. This may be accomplished by verifying that the type for the attribute is the same regardless of whether it is loaded by a loader that defines the referencing class or a loader that defines the referred class. If the constraint is not met, an error message is provided.

Abstract: A method for deploying an application file from a development station directly to a mobile device is provided. The development station is configured to execute operations including the receiving of a list of mobile devices registered with an integrated development environment (IDE) application that is executed on the development station. The method further includes selecting a mobile device from the list mobile devices and selecting the application file to be deployed to the mobile device. The deploying of the application file to the mobile device triggers methods of a plug-in application. The plug-in application is configured to execute operations including the establishing of a wireless connection between the development station and the mobile device. Upon establishing the wireless connection, the plug-in application triggers the transferring of the application file to the mobile device over the wireless connection.

Abstract: The present invention is a method for representation of sign in an encoding scheme. An embodiment of the present invention provides a variable bit length binary representation of the absolute value of integer data and then appends a single bit representing the sign of the original integer data. According to one embodiment, the present invention uses the trailing sign bit to specify the sign of the integer being coded. This scheme is much simpler to encode and decode than other schemes that use sign representations for variable-length bit sequences, especially for data that is roughly symmetric about zero, or can be efficiently mapped to this rough symmetry. In another embodiment, if the present invention is used on data sets where there is a most frequently occurring value, the locations of the most frequently recurring value are exhaustively cataloged through some other means, and the variable-length codes are modified to remove the representation of this value.

Abstract: Extending role scope in a directory server system. A directory server system comprises a directory server and a role mechanism. The directory server interacts with entries organized in a tree structure. The entries comprise user entries and role entries. The role entries define a role and have an associated scope defined from their location in the tree structure. The role mechanism is capable of attaching a role of an existing role entry to a user entry subject to a first condition comprising. The role mechanism is further capable of determining whether the existing role entry has extra data designating an extra scope, and, if so, of attaching a role of the existing role entry to a user entry subject to a second condition. The second condition comprises the role membership condition and the fact that the user entry belongs to the extra scope of the existing role entry.

Abstract: The handling of quoted material in an electronic environment is enhanced by using one or more quote bars. Quote bars permit quoted material to be treated as a single object and permit information about the source of a quote to be displayed. They also permit connection to a network address from which a quote may have originated. Using quote bars, the removal of copyright notices can be prevented.

Abstract: A file is striped across multiple filers, file servers or other devices, to create a sparsely striped multi-component file. Each filer stores one sparse component. In particular, each component physically stores only those stripes allocated to that component. The other stripes are represented as holes. Thus, instead of contiguously packing each component's stripes at the block level, each component is a file having the same logical structure. A component of a sparsely striped multi-component file can be easily converted to a mirror by filling in its holes. Similarly, a mirror can be easily converted to one component of a sparsely striped multi-component file by removing or ignoring it unallocated stripes. In either case, the layout or logical of the component does not need to be reconfigured.

Abstract: An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folded with local four-bit sums to efficiently generate a final sum output. The ALU implements ones complement subtraction by incorporating a subtraction select signal to invert each bit of a second operand. The ALU circuitry implements a push-pull methodology to improve performance.

Abstract: A method of a speculative tracing, including defining the speculative tracing using a plurality of probes, firing at least one of the plurality of probes defined by the speculative tracing, allocating at least one instance of a first speculative buffer arranged to transfer data to a first principal buffer, if one of the plurality of probes comprises a first speculation function, and determining a first state value associated with the first speculative buffer.

Abstract: A sense amplifier latch that is operable to interface with high common-mode input voltages with wide ranges for all process variations. The sense amplifier latch comprises a cross-coupled latch having first and second rail signals; a pre-charge device; an equalization device; pass devices for enabling input devices to receive pad and reference inputs. In the present invention, the input devices comprise push-pull impedance dividers are used to preserve the input difference voltage while dramatically lowering the common-mode output voltage. The outputs of the impedance dividers are fed to the cross-coupled latch of the sense amplifier using n-channel pass gates.

Abstract: Solutions to a value recycling problem that we define herein facilitate implementations of computer programs that may execute as multithreaded computations in multiprocessor computers, as well as implementations of related shared data structures. Some exploitations of the techniques described herein allow non-blocking, shared data structures to be implemented using standard dynamic allocation mechanisms (such as malloc and free). Indeed, we present several exemplary realizations of dynamic-sized, non-blocking shared data structures that are not prevented from future memory reclamation by thread failures and which depend (in some implementations) only on widely-available hardware support for synchronization. Some exploitations of the techniques described herein allow non-blocking, indeed even lock-free or wait-free, implementations of dynamic storage allocation for shared data structures.

Abstract: A server blade may be provided. The server blade may comprise a processor and storage. The server blade can further comprise an enclosure that encloses said processor and storage. The server blade can be configured as a field replaceable unit.

Abstract: A data structure is disclosed. The data structure includes a data descriptor record. In turn, the data descriptor record includes a type field, a base address field, an offset field, wherein the, and a length field. The type field may be configured, for example, to indicate a data structure type. The data structure type may be configured to assume a values indicating one of a contiguous buffer, a scatter-gather list and a linked list structure, among other such data structures. The base address field may be configured, for example, to store a base address, with the base address being a starting address of a secondary data structure associated with the data descriptor record. The offset field may be configured, for example, to indicate a starting address of data within a secondary data structure pointed to by a base address stored in the base address field.

Abstract: In one embodiment, a processor comprises a plurality of processor cores and an interconnect to which the plurality of processor cores are coupled. Each of the plurality of processor cores comprises at least one translation lookaside buffer (TLB). A first processor core is configured to broadcast a demap command on the interconnect responsive to executing a demap operation. The demap command identifies one or more translations to be invalidated in the TLBs, and remaining processor cores are configured to invalidate the translations in the respective TLBs. The remaining processor cores transmit a response to the first processor core, and the first processor core is configured to delay continued processing subsequent to the demap operation until the responses are received from each of the remaining processor cores.